Messages in this thread | | | From | Bjorn Helgaas <> | Date | Tue, 12 Mar 2013 10:21:24 -0600 | Subject | Re: [PATCH 2/2] PCI: fix system hang issue of Marvell SATA host controller |
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On Tue, Mar 12, 2013 at 3:22 AM, Xiangliang Yu <yuxiangl@marvell.com> wrote: > Hi, Myron >> > Now, the situation is like this: >> > I captured the PCIE trace with analyzer and found that 1st BE is 0x1111 >> > when >> > accessing IO port space. But 9125 spec has some limitation, and the BE >> > must >> > be >> > 0x0100, to access the 2nd byte only. So, the chip will go to bad. >> >> Great, this is new, interesting, data. Is the 9125 spec publicly >> accessible and/or could you elaborate on the "some limitation" >> comment? > 9125 spec is publicly accessible.
Please provide a URL for the spec.
>> A byte enable (BE) of 0x1111 suggests the CPU did a 32-bit I/O port >> read. Does the 9125 device only support one-byte I/O port accesses >> and when presented with larger request types it doesn't respond >> properly? > Yes, the hardware engineer had confirmed the situation.
Please provide a URL for the erratum describing this 9125 issue.
Bjorn
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