Messages in this thread | | | Subject | Re: [PATCH] drivers/block/xsysace - replace in(out)_8/in(out)_be16/in(out)_le16 with generic iowrite(read)8/16(be) | From | Benjamin Herrenschmidt <> | Date | Fri, 08 Feb 2013 08:15:43 +1100 |
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On Thu, 2013-02-07 at 16:44 +0000, Grant Likely wrote: > > I've just spent some quality time with a piece of paper, and I think > I've figured it out...
http://linuxplumbers.ubicast.tv/videos/big-and-little-endian-inside-out/
Watch the last part on IO busses....
This all has to do which which byte of the bus is the lowest byte *address* regardless of significance. That's how the wiring should be consistent between CPU and device, in order for a data port to work properly.
The data port then requires no swapping (which also means it works nicely with dumb DMA engines etc...)
Whether the registers need swapping or not depends on which half is the MSB, which is somewhat a semantically higher level than the bus transport, and depends on whether the device exposes them as BE or LE registers. But data ports are just "windows" to a byte stream and shouldn't be affected by endianess (again, unless you get a moron doing the HW which seems to be still too common).
There is only one right way to connect devices to CPUs basically, which is called byte address invariance, and preserves the order of bytes in term of byte addresses.
(Note that for busses that also carry addresses such as PCI, this can get tricky as you might need to have the lanes routed in a different order for address vs. data cycles).
Cheers, Ben.
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