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SubjectRe: [PATCH 05/73] ARM: ux500: Vsmps3 controlled by SysClkReq1
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On Mon, Feb 4, 2013 at 8:37 PM, Mark Brown
<broonie@opensource.wolfsonmicro.com> wrote:
> On Mon, Feb 04, 2013 at 11:53:20AM +0000, Lee Jones wrote:
>> Vsmps3 is put in HW control by SysClkReq1 at init. The
>> corresponding settings in suspend-force are removed.
>
> So, I've applied the patches up to here though I'm still reallly unhappy
> with this code - it seems clear from the comments that a lot of this
> stuff should be using regulator constraints to initialise. It would be
> good to move this stuff over to use the framework.

So I've briefly discussed it with Bengt at one point.

Basically what the ABx500 PMICs have is a sort of
logic network or table that you can set up to respond
autonomously to different "SysClkReq" signals.

Originally these signals were intended for gating
and ungating clocks but they are basically a boolean
"enable that resource I want" signals.

So it is not even primarily used for clocks, but
regulators. It will for example power them off/on
on that signal but also more elaborate stuff I think.

What is needed is some way to model that
electronic relationship into both the regulator
and clock subsystems (Ulf Hansson is working on
the ABx500 clocks as we speak.)

Maybe the actual place to have it would be
somewhere like drivers/mfd/ab8500-core.c.

Have you seen similar stuff in other PMICs?

Yours,
Linus Walleij


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