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SubjectRe: [PATCH v3] lpc_ich: fix gpio base and control offsets
> On Thu, Jan 24, 2013 at 02:52:39PM -0600, Aaron Sierra wrote:
> > In ICH5 and earlier the GPIOBASE and GPIOCTRL registers are found
> > at
> > offsets 0x58 and 0x5C, respectively. This patch allows GPIO access
> > to
> > properly be enabled (and disabled) for these chipsets.
> >
> > Signed-off-by: Agócs Pál <agocs.pal.86@gmail.com>
> > Signed-off-by: Aaron Sierra <asierra@xes-inc.com>
> > ---
> > drivers/mfd/lpc_ich.c | 109
> > ++++++++++++++++++++++++++++++++++---------------
> > 1 file changed, 76 insertions(+), 33 deletions(-)
> I applied this one to my for-next branch, but:
>
>
> > @@ -858,14 +874,35 @@ wdt_done:
> > static int lpc_ich_probe(struct pci_dev *dev,
> > const struct pci_device_id *id)
> > {
> > + struct lpc_ich_priv *priv;
> > int ret;
> > bool cell_added = false;
> >
> > - ret = lpc_ich_init_wdt(dev, id);
> > + priv = kmalloc(GFP_KERNEL, sizeof(struct lpc_ich_priv));
> > + if (!priv)
> > + return -ENOMEM;
> Could you please come back to me with a follow up patch that would
> convert this to the devm_kzalloc() API ?

Yeah, no problem.

-Aaron S.
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