| Date | Sun, 03 Feb 2013 15:48:13 +0100 | From | Ben Hutchings <> | Subject | [ 089/128] drm/i915: Correct the bit number for the MI_FLUSH_ENABLE. |
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3.2-stable review patch. If anyone has any objections, please let me know.
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From: Eric Anholt <eric@anholt.net>
commit fc74d8e01165b567922921d110b6d16320a61fa6 upstream.
Older specs claimed this was bit 11, but newer specs and the actual simulator code say it was bit 12. Regardless, we don't use MI_FLUSH, or try to enable it any more.
Signed-off-by: Eric Anholt <eric@anholt.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> [danvet: Anyone trying to use this bit, please read all the relevant discussions, it's epic.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Ben Hutchings <ben@decadent.org.uk> --- drivers/gpu/drm/i915/i915_reg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -399,7 +399,7 @@ #define MI_MODE 0x0209c # define VS_TIMER_DISPATCH (1 << 6) -# define MI_FLUSH_ENABLE (1 << 11) +# define MI_FLUSH_ENABLE (1 << 12) #define GEN6_GT_MODE 0x20d0 #define GEN6_GT_MODE_HI (1 << 9)
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