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SubjectRe: [PATCH 05/73] ARM: ux500: Vsmps3 controlled by SysClkReq1
On Tue, 05 Feb 2013, Mark Brown wrote:

> On Mon, Feb 04, 2013 at 10:21:36PM +0100, Linus Walleij wrote:
>
> > What is needed is some way to model that
> > electronic relationship into both the regulator
> > and clock subsystems (Ulf Hansson is working on
> > the ABx500 clocks as we speak.)
>
> > Maybe the actual place to have it would be
> > somewhere like drivers/mfd/ab8500-core.c.
>
> > Have you seen similar stuff in other PMICs?
>
> Yes, it's fairly common to at least have hardware enable signals. If
> what was going on was actually understood by the driver in some way it
> might be better but right now... Especially in a series like this it's
> really bad to just see loads of patches which boil down to "change the
> semi-documented magic value" - this just makes the series depressing to
> read.

Okay, I've just re-read this thread and it appears you're both talking
about different things.

Linus is talking about a discussion with Bengt regarding how these
strange sysclkreq thingies work. When I first read the code they
appear to be equivalent to GPIO regulators, but in actual fact the
hardware logic is different on enable/disable. So they probably don't
belong in regulator code at all.

Where as, Mark is complaining about how the regulators are initialised
by lots of magic register writes during init. Although, comments are
inserted for each of the values, they're by no means exhaustive and
aren't really even helpful if you don't have the uber-s3cr3t design
specification. What he would like to see is that most of this stuff
being handled by the framework. Some of this stuff is clearly only
setting voltages and power-states and the like.

I'd certainly be up for taking this on, but I think an in-depth
knowledge of the AB8500 regulator subsystem would be required.

--
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
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