Messages in this thread | | | Date | Tue, 12 Nov 2013 19:34:04 +0100 | From | Peter Zijlstra <> | Subject | Re: Does Itanium permit speculative stores? |
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On Tue, Nov 12, 2013 at 06:00:26PM +0000, Luck, Tony wrote: > The "ACCESS_ONCE" macro casts to volatile - which will make gcc generate > ordered "ld.acq" and "st.rel" instructions for your code snippets. So I think > you should be fine.
Hurm.. so:
+#define smp_store_release(p, v) \ +do { \ + compiletime_assert_atomic_type(*p); \ + switch (sizeof(*p)) { \ + case 4: \ + asm volatile ("st4.rel [%0]=%1" \ + : "=r" (p) : "r" (v) : "memory"); \ + break; \ + case 8: \ + asm volatile ("st8.rel [%0]=%1" \ + : "=r" (p) : "r" (v) : "memory"); \ + break; \ + } \ +} while (0) + +#define smp_load_acquire(p) \ +({ \ + typeof(*p) ___p1; \ + compiletime_assert_atomic_type(*p); \ + switch (sizeof(*p)) { \ + case 4: \ + asm volatile ("ld4.acq %0=[%1]" \ + : "=r" (___p1) : "r" (p) : "memory"); \ + break; \ + case 8: \ + asm volatile ("ld8.acq %0=[%1]" \ + : "=r" (___p1) : "r" (p) : "memory"); \ + break; \ + } \ + ___p1; \ +})
That all can be written as:
+#define smp_store_release(p, v) \ +do { \ + compiletime_assert_atomic_type(*p); \ + ACCESS_ONCE(*p) = (v); \ +} while (0) + +#define smp_load_acquire(p) \ +({ \ + typeof(*p) ___p1 = ACCESS_ONCE(*p); \ + compiletime_assert_atomic_type(*p); \ + ___p1; \ +})
On ia64? Totally much simpler!
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