lkml.org 
[lkml]   [2013]   [Oct]   [30]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
SubjectRe: [PATCH v2 4/6] edac: Document Krait L1/L2 EDAC driver binding
From
Date

On Oct 30, 2013, at 4:48 PM, Stephen Boyd wrote:

> On 10/30/13 14:45, Kumar Gala wrote:
>> On Oct 30, 2013, at 3:25 PM, Stephen Boyd wrote:
>>
>>> @@ -75,3 +77,50 @@ Example:
>>> reg = <0x101>;
>>> };
>>> };
>>> +
>>> +If the compatible string contains "qcom,krait" there shall be an interrupts
>>> +property containing the L1/CPU error interrupt number. There shall also be an
>> 'also be a'
>
> ok
>
>>
>>> +l2-cache node containing the following properties:
>> Is the L1 interrupt not per core L1 cache (even if they are OR together at PIC)?
>
> Yes it is per CPU. That is what the 0xf part of the cpus interrupts
> property is showing.

Than why not have it in each cpu node?

>>>
>>> + - compatible: Shall contain at least "cache"
>>> + - cache-level: Must be 2
>>> + - interrupts: Shall contain the L2 error interrupt
>>> +
>>> +Example:
>>> +
>>> + cpus {
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> + interrupts = <1 9 0xf04>;
>>> + compatible = "qcom,krait";
>>>


- k

--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation



\
 
 \ /
  Last update: 2013-10-30 23:21    [W:0.073 / U:7.732 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site