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SubjectRe: perf: PERF_EVENT_IOC_PERIOD on ARM vs everywhere else
On Mon, Oct 28, 2013 at 02:37:46AM +0000, Vince Weaver wrote:
> Hello

Hi Vince,

> it was pointed out to me that in the 3.7 kernel (more specifically,
> 3581fe0ef37ce12ac7a4f74831168352ae848edc ) a change was made in the
> ARM architecture to change how PERF_EVENT_IOC_PERIOD is handled.
>
> Unlike other architectures, post-3.7 ARM updates the period right away
> rather than waiting until the next overflow.
>
> I can't find any discussion as to why this change was made.

This was in response to complaints from both internal users and people on
public lists:

http://www.mail-archive.com/perfmon2-devel@lists.sourceforge.net/msg02657.html

I believe the scenario was something like:

(1) An instruction counter is set up to overflow after 200 instructions,
with a SIGIO handler to print some information. It is initially
disabled.

(2) At some point, the counter is enabled for 1 overflow (IOC_REFRESH)

(3) The counter eventually overflows and the SIGIO handler is triggered.
At this pointer the counter is disabled.

(4) The signal handler changes the period to 200k instructions using
IOC_PERIOD and enables the counter for a further overflow.

(5) SIGIO is taken after 200 instructions, rather than 200k.

> Should other architectures be updated to? I just wanted to find out the
> rationale for this before I update the manpage to reflect the difference
> in behaviors between architectures.

I don't want to be the `oddball' architecture (at least, not more than I am
already :), but I do find it tricky to follow the required semantics of perf
as opposed to `it happens to work this way', especially when so much of it
is buried in the various arch backends. So if somebody using the thing on
ARM has (what looks to me like) a valid issue, then I usually try and fix
it.

Cheers,

Will


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