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SubjectRe: [PATCH] x86: Run checksumming in parallel accross multiple alu's
If implemented properly adcx/adox should give additional speedup... that is the whole reason for their existence.

Neil Horman <> wrote:
>On Sat, Oct 12, 2013 at 03:29:24PM -0700, H. Peter Anvin wrote:
>> On 10/11/2013 09:51 AM, Neil Horman wrote:
>> > Sébastien Dugué reported to me that devices implementing ipoib
>(which don't have
>> > checksum offload hardware were spending a significant amount of
>time computing
>> > checksums. We found that by splitting the checksum computation
>into two
>> > separate streams, each skipping successive elements of the buffer
>being summed,
>> > we could parallelize the checksum operation accros multiple alus.
>Since neither
>> > chain is dependent on the result of the other, we get a speedup in
>execution (on
>> > hardware that has multiple alu's available, which is almost
>ubiquitous on x86),
>> > and only a negligible decrease on hardware that has only a single
>alu (an extra
>> > addition is introduced). Since addition in commutative, the result
>is the same,
>> > only faster
>> On hardware that implement ADCX/ADOX then you should also be able to
>> have additional streams interleaved since those instructions allow
>> dual carry chains.
>> -hpa
>I've been looking into this a bit more, and I'm a bit confused.
>According to
>by my read, this pair of instructions simply supports 2 carry bit
>allowing for two parallel execution paths through the cpu that won't
>block on
>one another. Its exactly the same as whats being done with the
>available addcq instruction, so theres no real speedup (that I can
>see). Since
>we'd either have to use the alternatives macro to support adcx/adox
>here or the
>old instruction set, it seems not overly worth the effort to support
>Or am I missing something?

Sent from my mobile phone. Please pardon brevity and lack of formatting.
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