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SubjectRe: [PATCH v4 05/15] clk: tegra: move some PLLC and PLLXC init to clk-pll.c
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Hi Peter,

> + val = readl_relaxed(clk_base + pll_params->base_reg);
> + val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
> +
> + if (val & BIT(30))

BIT(30) -> PLL_BASE_ENABLE?

> + WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
> + else {
> + val_iddq |= BIT(pll_params->iddq_bit_idx);
> + writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
> + }

Thanks,
Andrew


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