Messages in this thread Patch in this message | | | From | Jiang Liu <> | Subject | [PATCH v4 4/7] arm64: introduce aarch64_insn_gen_{nop|branch_imm}() helper functions | Date | Thu, 17 Oct 2013 14:19:37 +0800 |
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From: Jiang Liu <jiang.liu@huawei.com>
Introduce aarch64_insn_gen_{nop|branch_imm}() helper functions, which will be used to implement jump label on ARM64.
Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Cc: Jiang Liu <liuj97@gmail.com> --- arch/arm64/include/asm/insn.h | 7 +++++++ arch/arm64/kernel/insn.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+)
diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h index d62b601..ac129a8 100644 --- a/arch/arm64/include/asm/insn.h +++ b/arch/arm64/include/asm/insn.h @@ -94,6 +94,13 @@ static __always_inline void aarch64_insn_write(void *addr, u32 insn) enum aarch64_insn_encoding_class aarch64_get_insn_class(u32 insn); u32 aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type, u32 insn, u64 imm); +u32 aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr, + bool link); +static __always_inline u32 aarch64_insn_gen_nop(void) +{ + return aarch64_insn_get_nop_value(); +} + bool aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn); int aarch64_insn_patch_text_nosync(void *addrs[], u32 insns[], int cnt); diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c index 344d23ed..a59f71d 100644 --- a/arch/arm64/kernel/insn.c +++ b/arch/arm64/kernel/insn.c @@ -14,6 +14,7 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see <http://www.gnu.org/licenses/>. */ +#include <linux/bitops.h> #include <linux/compiler.h> #include <linux/kernel.h> #include <linux/smp.h> @@ -205,3 +206,30 @@ u32 aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type, return insn; } + +u32 aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr, bool link) +{ + u32 insn; + long offset; + + /* + * PC: A 64-bit Program Counter holding the address of the current + * instruction. A64 instructions may be word-aligned. + */ + BUG_ON((pc & 0x3) || (addr & 0x3)); + + /* + * B/BL support [-128M, 128M) offset + * ARM64 virtual address arrangement garantees all kernel and module + * texts are within +/-128M. + */ + offset = ((long)addr - (long)pc) >> 2; + BUG_ON(abs(offset) > BIT(25) || offset == BIT(25)); + + if (link) + insn = aarch64_insn_get_bl_value(); + else + insn = aarch64_insn_get_b_value(); + + return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_26, insn, offset); +} -- 1.8.1.2
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