Messages in this thread | | | From | Stephen GALLIMORE <> | Date | Thu, 10 Oct 2013 14:33:19 +0200 | Subject | RE: [PATCH v4 3/4] ARM: STi: Supply I2C configuration to STiH415 SoC |
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> -----Original Message----- > From: Maxime COQUELIN [mailto:maxime.coquelin@st.com] > Sent: 08 October 2013 17:43 >..... > + > + i2c@fed40000 { > + compatible = "st,comms-ssc-i2c"; > + reg = <0xfed40000 0x110>; > + interrupts = <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>;
This should specify level (high) triggered, not edge triggered, for our SoC integrations.
Note that level triggered is the default GIC setup and was therefore what was being used when you specified "0" for the flags previously.
> + clocks = <&CLKS_ICN_REG_0>; > + clock-names = "ssc"; > + clock-frequency = <400000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_i2c0_default>; > + > + status = "disabled"; > + };
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