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Subject[PATCH v7 09/18] perf/x86: export PEBS load latency threshold register to sysfs
Date
Make the PEBS Load Latency threshold register layout
and encoding visible to user level tools.

Signed-off-by: Stephane Eranian <eranian@google.com>
---
arch/x86/kernel/cpu/perf_event_intel.c | 3 +++
1 file changed, 3 insertions(+)

diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index f30027a..4ee1211 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -1756,6 +1756,8 @@ static void intel_pmu_flush_branch_stack(void)

PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");

+PMU_FORMAT_ATTR(ldlat, "config1:0-15");
+
static struct attribute *intel_arch3_formats_attr[] = {
&format_attr_event.attr,
&format_attr_umask.attr,
@@ -1766,6 +1768,7 @@ static struct attribute *intel_arch3_formats_attr[] = {
&format_attr_cmask.attr,

&format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */
+ &format_attr_ldlat.attr, /* PEBS load latency */
NULL,
};

--
1.7.9.5


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