| From | Greg Kroah-Hartman <> | Subject | [ 124/171] drm/radeon: fix ordering in pll picking on dce4+ | Date | Tue, 15 Jan 2013 14:44:49 -0800 |
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3.4-stable review patch. If anyone has any objections, please let me know.
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From: Alex Deucher <alexander.deucher@amd.com>
commit ecd67955fd4c8e66e4df312098989d5fa7da624c upstream.
No functional change, but re-order the cases so they evaluate properly due to the way the DCE macros work.
Noticed by kallisti5 on IRC.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Julien Cristau <jcristau@debian.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> --- drivers/gpu/drm/radeon/atombios_crtc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
--- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c @@ -1533,12 +1533,12 @@ static int radeon_atom_pick_pll(struct d * crtc virtual pixel clock. */ if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) { - if (ASIC_IS_DCE5(rdev)) - return ATOM_DCPLL; + if (rdev->clock.dp_extclk) + return ATOM_PPLL_INVALID; else if (ASIC_IS_DCE6(rdev)) return ATOM_PPLL0; - else if (rdev->clock.dp_extclk) - return ATOM_PPLL_INVALID; + else if (ASIC_IS_DCE5(rdev)) + return ATOM_DCPLL; } } }
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