Messages in this thread | | | Date | Tue, 25 Sep 2012 18:53:52 +0400 | From | Cyrill Gorcunov <> | Subject | Re: [PATCH 1/1] perf, Add support for Xeon-Phi PMU |
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On Tue, Sep 25, 2012 at 10:45:02AM -0400, Vince Weaver wrote: > > On Tue, 25 Sep 2012, Cyrill Gorcunov wrote: > > > So guys, if understand all things correctly it's supposed to use some > > -1/-2 as initial @config value for unsupported events, right? Vince, > > may not it be easier to use bit 19 as a flag of valid event and clear > > it when you write to msr, thus we will not have to change "zero is reserved" > > semantics (otoh i'm not sure if it won't become a problem somewhere in > > future with some new cpu :) > > Well, we wouldn't want to use a reserved bit. > In theory we could re-use bit 22 (enable) or bit 20 (APIC enable) > because those values should in theory be set elsewhere and could probably > be masked out at an appropriate place. > > Is -2 really a valid cache event on Pentium 4?
Nope, there can't be config with -2 as valid value. So we can use -2 if needed as far as I can tell (the -1 can't be valid as well).
> Though I admit patching all of the various PMU drivers to use -1/-2 rather > than 0/-1 will be a pain, especially as many of them just default to 0 > with no initialization currently.
Yup, but if it'll be needed I can tune up p4 code (thought i'll need some help in testing since i've no p4 cpu anymore).
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