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SubjectRe: [RFC][PATCH] perf, intel: Don't touch MSR_IA32_DEBUGCTLMSR from NMI context
On Wed, Sep 12, 2012 at 8:52 PM, Peter Zijlstra <> wrote:
> On Wed, 2012-09-12 at 20:50 +0200, Stephane Eranian wrote:
>> > As for BTS, it looks like we don't throttle the thing at all, so we
>> > shouldn't ever get to the asymmetric thing, right?
>> No you do, in the same function:
>> static void intel_pmu_disable_event(struct perf_event *event)
>> {
>> struct hw_perf_event *hwc = &event->hw;
>> struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
>> if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
>> intel_pmu_disable_bts();
>> intel_pmu_drain_bts_buffer();
>> return;
>> }
> Right, but the main event loop in intel_pmu_handle_irq() is over the
> MSR_CORE_PERF_GLOBAL_STATUS status bits, BTS is not included in those,
> so we'd never end up calling x86_pmu_stop() on the associated event.

True, it does not use a counter. But it interrupts when the buffer becomes full.
We catch this at the beginning of intel_pmu_handle_irq(). I think there is an
issue there with throtlling. Could be that the BTS buffer + workload could
caused PMU interrupts at a rate > max_rate. But yeah, it does not go
into the ovfl_status loop, so it cannot be stopped in an asymmetrical

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