[lkml]   [2012]   [Sep]   [12]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
SubjectRe: [RFC][PATCH] perf, intel: Don't touch MSR_IA32_DEBUGCTLMSR from NMI context
On Wed, 2012-09-12 at 18:42 +0200, Stephane Eranian wrote:
> We use FREEZE_LBR_ON_PMI to sync LBR data with counter overflows.
> That means, LBR is already frozen by the time we get to the handler. But
> that means we need to re-enable LBR when we leave the handler. I don't
> think EOI is going to magically re-enable it. So we need to touch DEBUGCTL
> in the irq handler.

Ah, so I do think EIO will re-enable LBR, also the handler is wrapped in
x86_pmu::{dis,en}able_all() which does end up calling
intel_pmu_lbr_{dis,en}able_all(). However that leaves the MSR in the
exact same state on exit as it was on enter, so that's not a problem for
the: read-modify-write change.

Its just that the x86_pmu::disable() for the throttle could leave the
MSR in a different state on exit than it entered with. This patch avoids

 \ /
  Last update: 2012-09-12 20:21    [W:0.095 / U:1.628 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site