Messages in this thread | | | Date | Mon, 30 Jul 2012 20:21:40 +0100 | From | Jamie Lokier <> | Subject | Re: [RFC] page-table walkers vs memory order |
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Paul E. McKenney wrote: > > Does some version of gcc, under the options which we insist upon, > > make such optimizations on any of the architectures which we support? > > Pretty much any production-quality compiler will do double-fetch > and old-value-reuse optimizations, the former especially on 32-bit > x86. I don't know of any production-quality compilers that do value > speculation, which would make the compiler act like DEC Alpha hardware, > and I would hope that if this does appear, (1) we would have warning > and (2) it could be turned off. But there has been a lot of work on > this topic, so we would be foolish to rule it out.
GCC documentation for IA-64:
-msched-ar-data-spec -mno-sched-ar-data-spec (En/Dis)able data speculative scheduling after reload. This results in generation of ld.a instructions and the corresponding check instructions (ld.c / chk.a). The default is 'enable'.
I don't know if that results in value speculation of the relevant kind.
-- Jamie
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