Messages in this thread | | | Subject | Re: [PATCH 2/2] [POWERPC] uprobes: powerpc port | From | Peter Zijlstra <> | Date | Wed, 06 Jun 2012 11:27:02 +0200 |
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On Wed, 2012-06-06 at 14:51 +0530, Ananth N Mavinakayanahalli wrote: > One TODO in this port compared to x86 is the uprobe abort_xol() logic. > x86 depends on the thread_struct.trap_nr (absent in powerpc) to determine > if a signal was caused when the uprobed instruction was single-stepped/ > emulated, in which case, we reset the instruction pointer to the probed > address and retry the probe again.
Another curious difference is that x86 uses an instruction decoder and contains massive tables to validate we can probe a particular instruction.
Can we probe all possible PPC instructions?
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