Messages in this thread | | | Date | Thu, 24 May 2012 21:54:29 +0800 | From | Alex Shi <> | Subject | Re: [PATCH v7 8/8] x86/tlb: just do tlb flush on one of siblings of SMT |
| |
On 05/24/2012 09:39 PM, Arjan van de Ven wrote:
> On 5/24/2012 6:23 AM, Peter Zijlstra wrote: >> On Thu, 2012-05-24 at 06:19 -0700, Andrew Lutomirski wrote: >>> >>> A decent heuristic might be to prefer idle SMT siblings for TLB >>> invalidation. I don't know what effect that would have on power >>> consumption (it would be rather bad if idling one SMT thread while the >>> other one is busy saves much power). > > we really really shouldn't do flushing of tlb's on only one half of SMT. > SMT sibblings have their own TLB pool at least on some of Intels chips.
That is also the biggest question I want to know. Actually, some documents, wiki said the SMT sibling just has process registers and interrupt part, no any tlb/l1 cache etc, (like intel's doc vol6iss1_hyper_threading_technology.pdf). And the patch runs well on NHM EP/WSM EP/NHM EX/SNB EP CPUs.
But hard to get such clearly per cpu info of SMT/HT, so, what the detailed Intel chips has 'TLB pool' on SMT?
> > Also, note that on anything sane, we flush the tlb's in software before > going to an Idle state, so that we don't have to wake idle cpus up to > flush their TLBs (except for "global tlbs", but those change very very > very rarely hopefully) > >> >> Right, I've never really understood how C-states and SMT go together. >> Arjan recently implied waking a thread sibling from C-state was >> 'expensive' which on first thought seems daft, the core is running >> already. > > in order to wake *anything* you need to send an IPI to it, it has to > exit the idle loop etc etc. It's not expensive-expensive, but it > certainly is not free either.
| |