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SubjectRe: [PATCH 3/3] arch/tile: tilegx PCI root complex support
Date
On Saturday 07 April 2012, Chris Metcalf wrote:
> This change implements PCIe root complex support for tilegx using
> the kernel support layer for accessing the TRIO hardware shim.
>
> Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>

Hi Chris,

I don't know if we discussed it during the initial merge, but I notice that the PIO
accessors (inb/outb and friends) are still not implemented in this patch. Normally
PIO can just be mapped into the MMIO address space, so that inb() becomes
a call to readb() with an offset on the address.

> +/*
> + * Second PCI initialization entry point, called by subsys_initcall.
> + *
> + * The controllers have been set up by the time we get here, by a call to
> + * tile_pci_init.
> + */
> +int __devinit pcibios_init(void)
> +{
> + resource_size_t offset;
> + int i;
> +
> + if (num_rc_controllers == 0 && num_ep_controllers == 0)
> + return 0;
> +
> + pr_info("PCI: Probing PCI hardware\n");
> +
> + /*
> + * We loop over all the TRIO shims and set up the MMIO mappings.
> + * This step can't be done in tile_pci_init because the MM subsystem
> + * hasn't been initialized then.
> + */
> + for (i = 0; i < TILEGX_NUM_TRIO; i++) {
> + gxio_trio_context_t *context = &trio_contexts[i];
> +
> + if (context->fd < 0)
> + continue;
> +
> + /*
> + * Map in the MMIO space for the MAC.
> + */
> + offset = 0;
> + context->mmio_base_mac =
> + iorpc_ioremap(context->fd, offset,
> + HV_TRIO_CONFIG_IOREMAP_SIZE);
> + if (context->mmio_base_mac == NULL) {
> + pr_err("PCI: MAC map failure on TRIO %d\n", i);
> +
> + hv_dev_close(context->fd);
> + context->fd = -1;
> + continue;
> + }
> + }
> +
> + /*
> + * Delay a bit in case devices aren't ready. Some devices are
> + * known to require at least 20ms here, but we use a more
> + * conservative value.
> + */
> + mdelay(250);

Using mdelay is generally considered very rude. Since you are not in atomic
context here, just use msleep() instead.

Arnd


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