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    Subject[PATCH v3 3/4] pinctrl: pinctrl-imx: add imx6q pinctrl driver
    Date
    From: Dong Aisheng <dong.aisheng@linaro.org>

    Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org>
    ---
    ChangeLog v1-v2:
    * add binding doc for pinctrl-imx6q
    * refactor the probe
    ---
    .../bindings/pinctrl/fsl,imx6q-pinctrl.txt | 1605 ++++++++++++++
    drivers/pinctrl/Kconfig | 8 +
    drivers/pinctrl/Makefile | 1 +
    drivers/pinctrl/pinctrl-imx6q.c | 2331 ++++++++++++++++++++
    4 files changed, 3945 insertions(+), 0 deletions(-)
    create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt
    create mode 100644 drivers/pinctrl/pinctrl-imx6q.c

    diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt
    new file mode 100644
    index 0000000..13d474f
    --- /dev/null
    +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt
    @@ -0,0 +1,1605 @@
    +* Freescale IMX6Q IOMUX Controller
    +
    +Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
    +and usage.
    +
    +Required properties:
    +- compatible: "fsl,imx6q-iomuxc"
    +- fsl,pins: two integers array, represents a group of pins mux and config
    + setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
    + pin working on a specific function, CONFIG is the pad setting value like
    + pull-up for this pin. Please refer to imx6q datasheet for the valid pad
    + config settings.
    +
    +See below for available PIN_FUNC_ID for imx6q:
    +MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 0
    +MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 1
    +MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 2
    +MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS 3
    +MX6Q_PAD_SD2_DAT1__KPP_COL_7 4
    +MX6Q_PAD_SD2_DAT1__GPIO_1_14 5
    +MX6Q_PAD_SD2_DAT1__CCM_WAIT 6
    +MX6Q_PAD_SD2_DAT1__ANATOP_TESTO_0 7
    +MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 8
    +MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 9
    +MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 10
    +MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD 11
    +MX6Q_PAD_SD2_DAT2__KPP_ROW_6 12
    +MX6Q_PAD_SD2_DAT2__GPIO_1_13 13
    +MX6Q_PAD_SD2_DAT2__CCM_STOP 14
    +MX6Q_PAD_SD2_DAT2__ANATOP_TESTO_1 15
    +MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 16
    +MX6Q_PAD_SD2_DAT0__ECSPI5_MISO 17
    +MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD 18
    +MX6Q_PAD_SD2_DAT0__KPP_ROW_7 19
    +MX6Q_PAD_SD2_DAT0__GPIO_1_15 20
    +MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT 21
    +MX6Q_PAD_SD2_DAT0__TESTO_2 22
    +MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA 23
    +MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC 24
    +MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK 25
    +MX6Q_PAD_RGMII_TXC__GPIO_6_19 26
    +MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0 27
    +MX6Q_PAD_RGMII_TXC__ANATOP_24M_OUT 28
    +MX6Q_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY 29
    +MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 30
    +MX6Q_PAD_RGMII_TD0__GPIO_6_20 31
    +MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1 32
    +MX6Q_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG 33
    +MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 34
    +MX6Q_PAD_RGMII_TD1__GPIO_6_21 35
    +MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2 36
    +MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP 37
    +MX6Q_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA 38
    +MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 39
    +MX6Q_PAD_RGMII_TD2__GPIO_6_22 40
    +MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3 41
    +MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP 42
    +MX6Q_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK 43
    +MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 44
    +MX6Q_PAD_RGMII_TD3__GPIO_6_23 45
    +MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4 46
    +MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA 47
    +MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 48
    +MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 49
    +MX6Q_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5 50
    +MX6Q_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY 51
    +MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 52
    +MX6Q_PAD_RGMII_RD0__GPIO_6_25 53
    +MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6 54
    +MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE 55
    +MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 56
    +MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 57
    +MX6Q_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7 58
    +MX6Q_PAD_RGMII_TX_CTL__ANATOP_REF_OUT 59
    +MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL 60
    +MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 61
    +MX6Q_PAD_RGMII_RD1__GPIO_6_27 62
    +MX6Q_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8 63
    +MX6Q_PAD_RGMII_RD1__SJC_FAIL 64
    +MX6Q_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA 65
    +MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 66
    +MX6Q_PAD_RGMII_RD2__GPIO_6_28 67
    +MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9 68
    +MX6Q_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK 69
    +MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 70
    +MX6Q_PAD_RGMII_RD3__GPIO_6_29 71
    +MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10 72
    +MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE 73
    +MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC 74
    +MX6Q_PAD_RGMII_RXC__GPIO_6_30 75
    +MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11 76
    +MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 77
    +MX6Q_PAD_EIM_A25__ECSPI4_SS1 78
    +MX6Q_PAD_EIM_A25__ECSPI2_RDY 79
    +MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 80
    +MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS 81
    +MX6Q_PAD_EIM_A25__GPIO_5_2 82
    +MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE 83
    +MX6Q_PAD_EIM_A25__PL301_PER1_HBURST_0 84
    +MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 85
    +MX6Q_PAD_EIM_EB2__ECSPI1_SS0 86
    +MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK 87
    +MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 88
    +MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL 89
    +MX6Q_PAD_EIM_EB2__GPIO_2_30 90
    +MX6Q_PAD_EIM_EB2__I2C2_SCL 91
    +MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 92
    +MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 93
    +MX6Q_PAD_EIM_D16__ECSPI1_SCLK 94
    +MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 95
    +MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 96
    +MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA 97
    +MX6Q_PAD_EIM_D16__GPIO_3_16 98
    +MX6Q_PAD_EIM_D16__I2C2_SDA 99
    +MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 100
    +MX6Q_PAD_EIM_D17__ECSPI1_MISO 101
    +MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 102
    +MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK 103
    +MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT 104
    +MX6Q_PAD_EIM_D17__GPIO_3_17 105
    +MX6Q_PAD_EIM_D17__I2C3_SCL 106
    +MX6Q_PAD_EIM_D17__PL301_PER1_HBURST_1 107
    +MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 108
    +MX6Q_PAD_EIM_D18__ECSPI1_MOSI 109
    +MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 110
    +MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 111
    +MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS 112
    +MX6Q_PAD_EIM_D18__GPIO_3_18 113
    +MX6Q_PAD_EIM_D18__I2C3_SDA 114
    +MX6Q_PAD_EIM_D18__PL301_PER1_HBURST_2 115
    +MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 116
    +MX6Q_PAD_EIM_D19__ECSPI1_SS1 117
    +MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 118
    +MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 119
    +MX6Q_PAD_EIM_D19__UART1_CTS 120
    +MX6Q_PAD_EIM_D19__GPIO_3_19 121
    +MX6Q_PAD_EIM_D19__EPIT1_EPITO 122
    +MX6Q_PAD_EIM_D19__PL301_PER1_HRESP 123
    +MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 124
    +MX6Q_PAD_EIM_D20__ECSPI4_SS0 125
    +MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 126
    +MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 127
    +MX6Q_PAD_EIM_D20__UART1_RTS 128
    +MX6Q_PAD_EIM_D20__GPIO_3_20 129
    +MX6Q_PAD_EIM_D20__EPIT2_EPITO 130
    +MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 131
    +MX6Q_PAD_EIM_D21__ECSPI4_SCLK 132
    +MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 133
    +MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 134
    +MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC 135
    +MX6Q_PAD_EIM_D21__GPIO_3_21 136
    +MX6Q_PAD_EIM_D21__I2C1_SCL 137
    +MX6Q_PAD_EIM_D21__SPDIF_IN1 138
    +MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 139
    +MX6Q_PAD_EIM_D22__ECSPI4_MISO 140
    +MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 141
    +MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 142
    +MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR 143
    +MX6Q_PAD_EIM_D22__GPIO_3_22 144
    +MX6Q_PAD_EIM_D22__SPDIF_OUT1 145
    +MX6Q_PAD_EIM_D22__PL301_PER1_HWRITE 146
    +MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 147
    +MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS 148
    +MX6Q_PAD_EIM_D23__UART3_CTS 149
    +MX6Q_PAD_EIM_D23__UART1_DCD 150
    +MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN 151
    +MX6Q_PAD_EIM_D23__GPIO_3_23 152
    +MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 153
    +MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 154
    +MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 155
    +MX6Q_PAD_EIM_EB3__ECSPI4_RDY 156
    +MX6Q_PAD_EIM_EB3__UART3_RTS 157
    +MX6Q_PAD_EIM_EB3__UART1_RI 158
    +MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC 159
    +MX6Q_PAD_EIM_EB3__GPIO_2_31 160
    +MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 161
    +MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 162
    +MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 163
    +MX6Q_PAD_EIM_D24__ECSPI4_SS2 164
    +MX6Q_PAD_EIM_D24__UART3_TXD 165
    +MX6Q_PAD_EIM_D24__ECSPI1_SS2 166
    +MX6Q_PAD_EIM_D24__ECSPI2_SS2 167
    +MX6Q_PAD_EIM_D24__GPIO_3_24 168
    +MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS 169
    +MX6Q_PAD_EIM_D24__UART1_DTR 170
    +MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 171
    +MX6Q_PAD_EIM_D25__ECSPI4_SS3 172
    +MX6Q_PAD_EIM_D25__UART3_RXD 173
    +MX6Q_PAD_EIM_D25__ECSPI1_SS3 174
    +MX6Q_PAD_EIM_D25__ECSPI2_SS3 175
    +MX6Q_PAD_EIM_D25__GPIO_3_25 176
    +MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC 177
    +MX6Q_PAD_EIM_D25__UART1_DSR 178
    +MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 179
    +MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 180
    +MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 181
    +MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 182
    +MX6Q_PAD_EIM_D26__UART2_TXD 183
    +MX6Q_PAD_EIM_D26__GPIO_3_26 184
    +MX6Q_PAD_EIM_D26__IPU1_SISG_2 185
    +MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 186
    +MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 187
    +MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 188
    +MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 189
    +MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 190
    +MX6Q_PAD_EIM_D27__UART2_RXD 191
    +MX6Q_PAD_EIM_D27__GPIO_3_27 192
    +MX6Q_PAD_EIM_D27__IPU1_SISG_3 193
    +MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 194
    +MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 195
    +MX6Q_PAD_EIM_D28__I2C1_SDA 196
    +MX6Q_PAD_EIM_D28__ECSPI4_MOSI 197
    +MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 198
    +MX6Q_PAD_EIM_D28__UART2_CTS 199
    +MX6Q_PAD_EIM_D28__GPIO_3_28 200
    +MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG 201
    +MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 202
    +MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 203
    +MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 204
    +MX6Q_PAD_EIM_D29__ECSPI4_SS0 205
    +MX6Q_PAD_EIM_D29__UART2_RTS 206
    +MX6Q_PAD_EIM_D29__GPIO_3_29 207
    +MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC 208
    +MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 209
    +MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 210
    +MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 211
    +MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 212
    +MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 213
    +MX6Q_PAD_EIM_D30__UART3_CTS 214
    +MX6Q_PAD_EIM_D30__GPIO_3_30 215
    +MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC 216
    +MX6Q_PAD_EIM_D30__PL301_PER1_HPROT_0 217
    +MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 218
    +MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 219
    +MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 220
    +MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 221
    +MX6Q_PAD_EIM_D31__UART3_RTS 222
    +MX6Q_PAD_EIM_D31__GPIO_3_31 223
    +MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR 224
    +MX6Q_PAD_EIM_D31__PL301_PER1_HPROT_1 225
    +MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 226
    +MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 227
    +MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 228
    +MX6Q_PAD_EIM_A24__IPU2_SISG_2 229
    +MX6Q_PAD_EIM_A24__IPU1_SISG_2 230
    +MX6Q_PAD_EIM_A24__GPIO_5_4 231
    +MX6Q_PAD_EIM_A24__PL301_PER1_HPROT_2 232
    +MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 233
    +MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 234
    +MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 235
    +MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 236
    +MX6Q_PAD_EIM_A23__IPU2_SISG_3 237
    +MX6Q_PAD_EIM_A23__IPU1_SISG_3 238
    +MX6Q_PAD_EIM_A23__GPIO_6_6 239
    +MX6Q_PAD_EIM_A23__PL301_PER1_HPROT_3 240
    +MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 241
    +MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 242
    +MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 243
    +MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 244
    +MX6Q_PAD_EIM_A22__GPIO_2_16 245
    +MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 246
    +MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 247
    +MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 248
    +MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 249
    +MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 250
    +MX6Q_PAD_EIM_A21__RESERVED_RESERVED 251
    +MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18 252
    +MX6Q_PAD_EIM_A21__GPIO_2_17 253
    +MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 254
    +MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 255
    +MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 256
    +MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 257
    +MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 258
    +MX6Q_PAD_EIM_A20__RESERVED_RESERVED 259
    +MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19 260
    +MX6Q_PAD_EIM_A20__GPIO_2_18 261
    +MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 262
    +MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 263
    +MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 264
    +MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 265
    +MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 266
    +MX6Q_PAD_EIM_A19__RESERVED_RESERVED 267
    +MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20 268
    +MX6Q_PAD_EIM_A19__GPIO_2_19 269
    +MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 270
    +MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 271
    +MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 272
    +MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 273
    +MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 274
    +MX6Q_PAD_EIM_A18__RESERVED_RESERVED 275
    +MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21 276
    +MX6Q_PAD_EIM_A18__GPIO_2_20 277
    +MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 278
    +MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 279
    +MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 280
    +MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 281
    +MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 282
    +MX6Q_PAD_EIM_A17__RESERVED_RESERVED 283
    +MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22 284
    +MX6Q_PAD_EIM_A17__GPIO_2_21 285
    +MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 286
    +MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 287
    +MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 288
    +MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK 289
    +MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK 290
    +MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23 291
    +MX6Q_PAD_EIM_A16__GPIO_2_22 292
    +MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 293
    +MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 294
    +MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 295
    +MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 296
    +MX6Q_PAD_EIM_CS0__ECSPI2_SCLK 297
    +MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24 298
    +MX6Q_PAD_EIM_CS0__GPIO_2_23 299
    +MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 300
    +MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 301
    +MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 302
    +MX6Q_PAD_EIM_CS1__ECSPI2_MOSI 303
    +MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25 304
    +MX6Q_PAD_EIM_CS1__GPIO_2_24 305
    +MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 306
    +MX6Q_PAD_EIM_OE__WEIM_WEIM_OE 307
    +MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 308
    +MX6Q_PAD_EIM_OE__ECSPI2_MISO 309
    +MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26 310
    +MX6Q_PAD_EIM_OE__GPIO_2_25 311
    +MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 312
    +MX6Q_PAD_EIM_RW__WEIM_WEIM_RW 313
    +MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 314
    +MX6Q_PAD_EIM_RW__ECSPI2_SS0 315
    +MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27 316
    +MX6Q_PAD_EIM_RW__GPIO_2_26 317
    +MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 318
    +MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 319
    +MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA 320
    +MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 321
    +MX6Q_PAD_EIM_LBA__ECSPI2_SS1 322
    +MX6Q_PAD_EIM_LBA__GPIO_2_27 323
    +MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 324
    +MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 325
    +MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 326
    +MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 327
    +MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 328
    +MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0 329
    +MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY 330
    +MX6Q_PAD_EIM_EB0__GPIO_2_28 331
    +MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 332
    +MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 333
    +MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 334
    +MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 335
    +MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 336
    +MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1 337
    +MX6Q_PAD_EIM_EB1__GPIO_2_29 338
    +MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 339
    +MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 340
    +MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 341
    +MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 342
    +MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 343
    +MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2 344
    +MX6Q_PAD_EIM_DA0__GPIO_3_0 345
    +MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 346
    +MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 347
    +MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 348
    +MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 349
    +MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 350
    +MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3 351
    +MX6Q_PAD_EIM_DA1__USBPHY1_TX_LS_MODE 352
    +MX6Q_PAD_EIM_DA1__GPIO_3_1 353
    +MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 354
    +MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 355
    +MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 356
    +MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 357
    +MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 358
    +MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4 359
    +MX6Q_PAD_EIM_DA2__USBPHY1_TX_HS_MODE 360
    +MX6Q_PAD_EIM_DA2__GPIO_3_2 361
    +MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 362
    +MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 363
    +MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 364
    +MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 365
    +MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 366
    +MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5 367
    +MX6Q_PAD_EIM_DA3__USBPHY1_TX_HIZ 368
    +MX6Q_PAD_EIM_DA3__GPIO_3_3 369
    +MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 370
    +MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 371
    +MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 372
    +MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 373
    +MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 374
    +MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6 375
    +MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN 376
    +MX6Q_PAD_EIM_DA4__GPIO_3_4 377
    +MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 378
    +MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 379
    +MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 380
    +MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 381
    +MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 382
    +MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7 383
    +MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP 384
    +MX6Q_PAD_EIM_DA5__GPIO_3_5 385
    +MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 386
    +MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 387
    +MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 388
    +MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 389
    +MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 390
    +MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8 391
    +MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN 392
    +MX6Q_PAD_EIM_DA6__GPIO_3_6 393
    +MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 394
    +MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 395
    +MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 396
    +MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 397
    +MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 398
    +MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9 399
    +MX6Q_PAD_EIM_DA7__GPIO_3_7 400
    +MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 401
    +MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 402
    +MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 403
    +MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 404
    +MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 405
    +MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10 406
    +MX6Q_PAD_EIM_DA8__GPIO_3_8 407
    +MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 408
    +MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 409
    +MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 410
    +MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 411
    +MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 412
    +MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11 413
    +MX6Q_PAD_EIM_DA9__GPIO_3_9 414
    +MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 415
    +MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 416
    +MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 417
    +MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 418
    +MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 419
    +MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12 420
    +MX6Q_PAD_EIM_DA10__GPIO_3_10 421
    +MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 422
    +MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 423
    +MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 424
    +MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 425
    +MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC 426
    +MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13 427
    +MX6Q_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6 428
    +MX6Q_PAD_EIM_DA11__GPIO_3_11 429
    +MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 430
    +MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 431
    +MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 432
    +MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 433
    +MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC 434
    +MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14 435
    +MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3 436
    +MX6Q_PAD_EIM_DA12__GPIO_3_12 437
    +MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 438
    +MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 439
    +MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 440
    +MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS 441
    +MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK 442
    +MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15 443
    +MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4 444
    +MX6Q_PAD_EIM_DA13__GPIO_3_13 445
    +MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 446
    +MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 447
    +MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 448
    +MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS 449
    +MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK 450
    +MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16 451
    +MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5 452
    +MX6Q_PAD_EIM_DA14__GPIO_3_14 453
    +MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 454
    +MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 455
    +MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 456
    +MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 457
    +MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 458
    +MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17 459
    +MX6Q_PAD_EIM_DA15__GPIO_3_15 460
    +MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 461
    +MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 462
    +MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT 463
    +MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B 464
    +MX6Q_PAD_EIM_WAIT__GPIO_5_0 465
    +MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 466
    +MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 467
    +MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK 468
    +MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 469
    +MX6Q_PAD_EIM_BCLK__GPIO_6_31 470
    +MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 471
    +MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DSP_CLK 472
    +MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DSP_CLK 473
    +MX6Q_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 474
    +MX6Q_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 475
    +MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 476
    +MX6Q_PAD_DI0_DISP_CLK__MMDC_DEBUG_0 477
    +MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 478
    +MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 479
    +MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC 480
    +MX6Q_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 481
    +MX6Q_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 482
    +MX6Q_PAD_DI0_PIN15__GPIO_4_17 483
    +MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 484
    +MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 485
    +MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 486
    +MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD 487
    +MX6Q_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 488
    +MX6Q_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2 489
    +MX6Q_PAD_DI0_PIN2__GPIO_4_18 490
    +MX6Q_PAD_DI0_PIN2__MMDC_DEBUG_2 491
    +MX6Q_PAD_DI0_PIN2__PL301_PER1_HADDR_9 492
    +MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 493
    +MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 494
    +MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS 495
    +MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 496
    +MX6Q_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3 497
    +MX6Q_PAD_DI0_PIN3__GPIO_4_19 498
    +MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 499
    +MX6Q_PAD_DI0_PIN3__PL301_PER1_HADDR_10 500
    +MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 501
    +MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 502
    +MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD 503
    +MX6Q_PAD_DI0_PIN4__USDHC1_WP 504
    +MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD 505
    +MX6Q_PAD_DI0_PIN4__GPIO_4_20 506
    +MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 507
    +MX6Q_PAD_DI0_PIN4__PL301_PER1_HADDR_11 508
    +MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 509
    +MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 510
    +MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK 511
    +MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 512
    +MX6Q_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN 513
    +MX6Q_PAD_DISP0_DAT0__GPIO_4_21 514
    +MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 515
    +MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 516
    +MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 517
    +MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI 518
    +MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 519
    +MX6Q_PAD_DISP0_DAT1__SDMA_DBG_EVT_CHNSL 520
    +MX6Q_PAD_DISP0_DAT1__GPIO_4_22 521
    +MX6Q_PAD_DISP0_DAT1__MMDC_DEBUG_6 522
    +MX6Q_PAD_DISP0_DAT1__PL301_PER1_HADR_12 523
    +MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 524
    +MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 525
    +MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO 526
    +MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 527
    +MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE 528
    +MX6Q_PAD_DISP0_DAT2__GPIO_4_23 529
    +MX6Q_PAD_DISP0_DAT2__MMDC_DEBUG_7 530
    +MX6Q_PAD_DISP0_DAT2__PL301_PER1_HADR_13 531
    +MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 532
    +MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 533
    +MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 534
    +MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 535
    +MX6Q_PAD_DISP0_DAT3__SDMA_DBG_BUS_ERROR 536
    +MX6Q_PAD_DISP0_DAT3__GPIO_4_24 537
    +MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 538
    +MX6Q_PAD_DISP0_DAT3__PL301_PER1_HADR_14 539
    +MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 540
    +MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 541
    +MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 542
    +MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4 543
    +MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB 544
    +MX6Q_PAD_DISP0_DAT4__GPIO_4_25 545
    +MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 546
    +MX6Q_PAD_DISP0_DAT4__PL301_PER1_HADR_15 547
    +MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 548
    +MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 549
    +MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 550
    +MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS 551
    +MX6Q_PAD_DISP0_DAT5__SDMA_DBG_MCH_DMBUS 552
    +MX6Q_PAD_DISP0_DAT5__GPIO_4_26 553
    +MX6Q_PAD_DISP0_DAT5__MMDC_DEBUG_10 554
    +MX6Q_PAD_DISP0_DAT5__PL301_PER1_HADR_16 555
    +MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 556
    +MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 557
    +MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 558
    +MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC 559
    +MX6Q_PAD_DISP0_DAT6__SDMA_DBG_RTBUF_WRT 560
    +MX6Q_PAD_DISP0_DAT6__GPIO_4_27 561
    +MX6Q_PAD_DISP0_DAT6__MMDC_DEBUG_11 562
    +MX6Q_PAD_DISP0_DAT6__PL301_PER1_HADR_17 563
    +MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 564
    +MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 565
    +MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY 566
    +MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 567
    +MX6Q_PAD_DISP0_DAT7__SDMA_DBG_EVT_CHN_0 568
    +MX6Q_PAD_DISP0_DAT7__GPIO_4_28 569
    +MX6Q_PAD_DISP0_DAT7__MMDC_DEBUG_12 570
    +MX6Q_PAD_DISP0_DAT7__PL301_PER1_HADR_18 571
    +MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 572
    +MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 573
    +MX6Q_PAD_DISP0_DAT8__PWM1_PWMO 574
    +MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B 575
    +MX6Q_PAD_DISP0_DAT8__SDMA_DBG_EVT_CHN_1 576
    +MX6Q_PAD_DISP0_DAT8__GPIO_4_29 577
    +MX6Q_PAD_DISP0_DAT8__MMDC_DEBUG_13 578
    +MX6Q_PAD_DISP0_DAT8__PL301_PER1_HADR_19 579
    +MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 580
    +MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 581
    +MX6Q_PAD_DISP0_DAT9__PWM2_PWMO 582
    +MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B 583
    +MX6Q_PAD_DISP0_DAT9__SDMA_DBG_EVT_CHN_2 584
    +MX6Q_PAD_DISP0_DAT9__GPIO_4_30 585
    +MX6Q_PAD_DISP0_DAT9__MMDC_DEBUG_14 586
    +MX6Q_PAD_DISP0_DAT9__PL301_PER1_HADR_20 587
    +MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 588
    +MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 589
    +MX6Q_PAD_DISP0_DAT10__USDHC1_DBG_6 590
    +MX6Q_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 591
    +MX6Q_PAD_DISP0_DAT10__GPIO_4_31 592
    +MX6Q_PAD_DISP0_DAT10__MMDC_DEBUG_15 593
    +MX6Q_PAD_DISP0_DAT10__PL301_PER1_HADR21 594
    +MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 595
    +MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 596
    +MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 597
    +MX6Q_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 598
    +MX6Q_PAD_DISP0_DAT11__GPIO_5_5 599
    +MX6Q_PAD_DISP0_DAT11__MMDC_DEBUG_16 600
    +MX6Q_PAD_DISP0_DAT11__PL301_PER1_HADR22 601
    +MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 602
    +MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 603
    +MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED 604
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    +MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 610
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    +MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 624
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    +MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 647
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    +MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS 650
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    +MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 655
    +MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK 656
    +MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD 657
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    +MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 663
    +MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK 664
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    +MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 671
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    +MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 679
    +MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO 680
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    +MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 686
    +MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 687
    +MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 688
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    +MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED 694
    +MX6Q_PAD_ENET_MDIO__ENET_MDIO 695
    +MX6Q_PAD_ENET_MDIO__ESAI1_SCKR 696
    +MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEV3 697
    +MX6Q_PAD_ENET_MDIO__ENET_1588_EVT1_OUT 698
    +MX6Q_PAD_ENET_MDIO__GPIO_1_22 699
    +MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK 700
    +MX6Q_PAD_ENET_REF_CLK__RESERVED_RSRVED 701
    +MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 702
    +MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR 703
    +MX6Q_PAD_ENET_REF_CLK__SDMA_DBGBUS_DEV4 704
    +MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 705
    +MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK 706
    +MX6Q_PAD_ENET_REF_CLK__USBPHY1_RX_SQH 707
    +MX6Q_PAD_ENET_RX_ER__ENET_RX_ER 708
    +MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR 709
    +MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 710
    +MX6Q_PAD_ENET_RX_ER__ENET_1588_EVT2_OUT 711
    +MX6Q_PAD_ENET_RX_ER__GPIO_1_24 712
    +MX6Q_PAD_ENET_RX_ER__PHY_TDI 713
    +MX6Q_PAD_ENET_RX_ER__USBPHY1_RX_HS_RXD 714
    +MX6Q_PAD_ENET_CRS_DV__RESERVED_RSRVED 715
    +MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN 716
    +MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT 717
    +MX6Q_PAD_ENET_CRS_DV__SPDIF_EXTCLK 718
    +MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 719
    +MX6Q_PAD_ENET_CRS_DV__PHY_TDO 720
    +MX6Q_PAD_ENET_CRS_DV__USBPHY1_RX_FS_RXD 721
    +MX6Q_PAD_ENET_RXD1__MLB_MLBSIG 722
    +MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 723
    +MX6Q_PAD_ENET_RXD1__ESAI1_FST 724
    +MX6Q_PAD_ENET_RXD1__ENET_1588_EVT3_OUT 725
    +MX6Q_PAD_ENET_RXD1__GPIO_1_26 726
    +MX6Q_PAD_ENET_RXD1__PHY_TCK 727
    +MX6Q_PAD_ENET_RXD1__USBPHY1_RX_DISCON 728
    +MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT 729
    +MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 730
    +MX6Q_PAD_ENET_RXD0__ESAI1_HCKT 731
    +MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 732
    +MX6Q_PAD_ENET_RXD0__GPIO_1_27 733
    +MX6Q_PAD_ENET_RXD0__PHY_TMS 734
    +MX6Q_PAD_ENET_RXD0__USBPHY1_PLL_CK20DIV 735
    +MX6Q_PAD_ENET_TX_EN__RESERVED_RSRVED 736
    +MX6Q_PAD_ENET_TX_EN__ENET_TX_EN 737
    +MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 738
    +MX6Q_PAD_ENET_TX_EN__GPIO_1_28 739
    +MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI 740
    +MX6Q_PAD_ENET_TX_EN__USBPHY2_RX_SQH 741
    +MX6Q_PAD_ENET_TXD1__MLB_MLBCLK 742
    +MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 743
    +MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 744
    +MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 745
    +MX6Q_PAD_ENET_TXD1__GPIO_1_29 746
    +MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO 747
    +MX6Q_PAD_ENET_TXD1__USBPHY2_RX_HS_RXD 748
    +MX6Q_PAD_ENET_TXD0__RESERVED_RSRVED 749
    +MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 750
    +MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 751
    +MX6Q_PAD_ENET_TXD0__GPIO_1_30 752
    +MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK 753
    +MX6Q_PAD_ENET_TXD0__USBPHY2_RX_FS_RXD 754
    +MX6Q_PAD_ENET_MDC__MLB_MLBDAT 755
    +MX6Q_PAD_ENET_MDC__ENET_MDC 756
    +MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 757
    +MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN 758
    +MX6Q_PAD_ENET_MDC__GPIO_1_31 759
    +MX6Q_PAD_ENET_MDC__SATA_PHY_TMS 760
    +MX6Q_PAD_ENET_MDC__USBPHY2_RX_DISCON 761
    +MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 762
    +MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 763
    +MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 764
    +MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 765
    +MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 766
    +MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 767
    +MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 768
    +MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 769
    +MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 770
    +MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 771
    +MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 772
    +MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 773
    +MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 774
    +MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 775
    +MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 776
    +MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 777
    +MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 778
    +MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 779
    +MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 780
    +MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 781
    +MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 782
    +MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 783
    +MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 784
    +MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 785
    +MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 786
    +MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 787
    +MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 788
    +MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 789
    +MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 790
    +MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 791
    +MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 792
    +MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 793
    +MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 794
    +MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 795
    +MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 796
    +MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 797
    +MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 798
    +MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 799
    +MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 800
    +MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 801
    +MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 802
    +MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 803
    +MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 804
    +MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 805
    +MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 806
    +MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 807
    +MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 808
    +MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 809
    +MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 810
    +MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 811
    +MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 812
    +MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 813
    +MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 814
    +MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 815
    +MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 816
    +MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 817
    +MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS 818
    +MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 819
    +MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 820
    +MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS 821
    +MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET 822
    +MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 823
    +MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 824
    +MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 825
    +MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 826
    +MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 827
    +MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 828
    +MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 829
    +MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 830
    +MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 831
    +MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE 832
    +MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 833
    +MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 834
    +MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 835
    +MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 836
    +MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 837
    +MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 838
    +MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 839
    +MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 840
    +MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 841
    +MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 842
    +MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 843
    +MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 844
    +MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 845
    +MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 846
    +MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 847
    +MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 848
    +MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 849
    +MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 850
    +MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 851
    +MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 852
    +MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 853
    +MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 854
    +MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 855
    +MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 856
    +MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 857
    +MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 858
    +MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 859
    +MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 860
    +MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 861
    +MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 862
    +MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 863
    +MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 864
    +MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 865
    +MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 866
    +MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 867
    +MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 868
    +MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 869
    +MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 870
    +MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 871
    +MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 872
    +MX6Q_PAD_KEY_COL0__ECSPI1_SCLK 873
    +MX6Q_PAD_KEY_COL0__ENET_RDATA_3 874
    +MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC 875
    +MX6Q_PAD_KEY_COL0__KPP_COL_0 876
    +MX6Q_PAD_KEY_COL0__UART4_TXD 877
    +MX6Q_PAD_KEY_COL0__GPIO_4_6 878
    +MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT 879
    +MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST 880
    +MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI 881
    +MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 882
    +MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 883
    +MX6Q_PAD_KEY_ROW0__KPP_ROW_0 884
    +MX6Q_PAD_KEY_ROW0__UART4_RXD 885
    +MX6Q_PAD_KEY_ROW0__GPIO_4_7 886
    +MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT 887
    +MX6Q_PAD_KEY_ROW0__PL301_PER1_HADR_0 888
    +MX6Q_PAD_KEY_COL1__ECSPI1_MISO 889
    +MX6Q_PAD_KEY_COL1__ENET_MDIO 890
    +MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 891
    +MX6Q_PAD_KEY_COL1__KPP_COL_1 892
    +MX6Q_PAD_KEY_COL1__UART5_TXD 893
    +MX6Q_PAD_KEY_COL1__GPIO_4_8 894
    +MX6Q_PAD_KEY_COL1__USDHC1_VSELECT 895
    +MX6Q_PAD_KEY_COL1__PL301MX_PER1_HADR_1 896
    +MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 897
    +MX6Q_PAD_KEY_ROW1__ENET_COL 898
    +MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 899
    +MX6Q_PAD_KEY_ROW1__KPP_ROW_1 900
    +MX6Q_PAD_KEY_ROW1__UART5_RXD 901
    +MX6Q_PAD_KEY_ROW1__GPIO_4_9 902
    +MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT 903
    +MX6Q_PAD_KEY_ROW1__PL301_PER1_HADDR_2 904
    +MX6Q_PAD_KEY_COL2__ECSPI1_SS1 905
    +MX6Q_PAD_KEY_COL2__ENET_RDATA_2 906
    +MX6Q_PAD_KEY_COL2__CAN1_TXCAN 907
    +MX6Q_PAD_KEY_COL2__KPP_COL_2 908
    +MX6Q_PAD_KEY_COL2__ENET_MDC 909
    +MX6Q_PAD_KEY_COL2__GPIO_4_10 910
    +MX6Q_PAD_KEY_COL2__USBOH3_H1_PWRCTL_WKP 911
    +MX6Q_PAD_KEY_COL2__PL301_PER1_HADDR_3 912
    +MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 913
    +MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 914
    +MX6Q_PAD_KEY_ROW2__CAN1_RXCAN 915
    +MX6Q_PAD_KEY_ROW2__KPP_ROW_2 916
    +MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT 917
    +MX6Q_PAD_KEY_ROW2__GPIO_4_11 918
    +MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 919
    +MX6Q_PAD_KEY_ROW2__PL301_PER1_HADR_4 920
    +MX6Q_PAD_KEY_COL3__ECSPI1_SS3 921
    +MX6Q_PAD_KEY_COL3__ENET_CRS 922
    +MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL 923
    +MX6Q_PAD_KEY_COL3__KPP_COL_3 924
    +MX6Q_PAD_KEY_COL3__I2C2_SCL 925
    +MX6Q_PAD_KEY_COL3__GPIO_4_12 926
    +MX6Q_PAD_KEY_COL3__SPDIF_IN1 927
    +MX6Q_PAD_KEY_COL3__PL301_PER1_HADR_5 928
    +MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT 929
    +MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK 930
    +MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 931
    +MX6Q_PAD_KEY_ROW3__KPP_ROW_3 932
    +MX6Q_PAD_KEY_ROW3__I2C2_SDA 933
    +MX6Q_PAD_KEY_ROW3__GPIO_4_13 934
    +MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT 935
    +MX6Q_PAD_KEY_ROW3__PL301_PER1_HADR_6 936
    +MX6Q_PAD_KEY_COL4__CAN2_TXCAN 937
    +MX6Q_PAD_KEY_COL4__IPU1_SISG_4 938
    +MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC 939
    +MX6Q_PAD_KEY_COL4__KPP_COL_4 940
    +MX6Q_PAD_KEY_COL4__UART5_RTS 941
    +MX6Q_PAD_KEY_COL4__GPIO_4_14 942
    +MX6Q_PAD_KEY_COL4__MMDC_DEBUG_49 943
    +MX6Q_PAD_KEY_COL4__PL301_PER1_HADDR_7 944
    +MX6Q_PAD_KEY_ROW4__CAN2_RXCAN 945
    +MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 946
    +MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR 947
    +MX6Q_PAD_KEY_ROW4__KPP_ROW_4 948
    +MX6Q_PAD_KEY_ROW4__UART5_CTS 949
    +MX6Q_PAD_KEY_ROW4__GPIO_4_15 950
    +MX6Q_PAD_KEY_ROW4__MMDC_DEBUG_50 951
    +MX6Q_PAD_KEY_ROW4__PL301_PER1_HADR_8 952
    +MX6Q_PAD_GPIO_0__CCM_CLKO 953
    +MX6Q_PAD_GPIO_0__KPP_COL_5 954
    +MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK 955
    +MX6Q_PAD_GPIO_0__EPIT1_EPITO 956
    +MX6Q_PAD_GPIO_0__GPIO_1_0 957
    +MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR 958
    +MX6Q_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5 959
    +MX6Q_PAD_GPIO_1__ESAI1_SCKR 960
    +MX6Q_PAD_GPIO_1__WDOG2_WDOG_B 961
    +MX6Q_PAD_GPIO_1__KPP_ROW_5 962
    +MX6Q_PAD_GPIO_1__PWM2_PWMO 963
    +MX6Q_PAD_GPIO_1__GPIO_1_1 964
    +MX6Q_PAD_GPIO_1__USDHC1_CD 965
    +MX6Q_PAD_GPIO_1__SRC_TESTER_ACK 966
    +MX6Q_PAD_GPIO_9__ESAI1_FSR 967
    +MX6Q_PAD_GPIO_9__WDOG1_WDOG_B 968
    +MX6Q_PAD_GPIO_9__KPP_COL_6 969
    +MX6Q_PAD_GPIO_9__CCM_REF_EN_B 970
    +MX6Q_PAD_GPIO_9__PWM1_PWMO 971
    +MX6Q_PAD_GPIO_9__GPIO_1_9 972
    +MX6Q_PAD_GPIO_9__USDHC1_WP 973
    +MX6Q_PAD_GPIO_9__SRC_EARLY_RST 974
    +MX6Q_PAD_GPIO_3__ESAI1_HCKR 975
    +MX6Q_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0 976
    +MX6Q_PAD_GPIO_3__I2C3_SCL 977
    +MX6Q_PAD_GPIO_3__ANATOP_24M_OUT 978
    +MX6Q_PAD_GPIO_3__CCM_CLKO2 979
    +MX6Q_PAD_GPIO_3__GPIO_1_3 980
    +MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC 981
    +MX6Q_PAD_GPIO_3__MLB_MLBCLK 982
    +MX6Q_PAD_GPIO_6__ESAI1_SCKT 983
    +MX6Q_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1 984
    +MX6Q_PAD_GPIO_6__I2C3_SDA 985
    +MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 986
    +MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB 987
    +MX6Q_PAD_GPIO_6__GPIO_1_6 988
    +MX6Q_PAD_GPIO_6__USDHC2_LCTL 989
    +MX6Q_PAD_GPIO_6__MLB_MLBSIG 990
    +MX6Q_PAD_GPIO_2__ESAI1_FST 991
    +MX6Q_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2 992
    +MX6Q_PAD_GPIO_2__KPP_ROW_6 993
    +MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 994
    +MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 995
    +MX6Q_PAD_GPIO_2__GPIO_1_2 996
    +MX6Q_PAD_GPIO_2__USDHC2_WP 997
    +MX6Q_PAD_GPIO_2__MLB_MLBDAT 998
    +MX6Q_PAD_GPIO_4__ESAI1_HCKT 999
    +MX6Q_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3 1000
    +MX6Q_PAD_GPIO_4__KPP_COL_7 1001
    +MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 1002
    +MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 1003
    +MX6Q_PAD_GPIO_4__GPIO_1_4 1004
    +MX6Q_PAD_GPIO_4__USDHC2_CD 1005
    +MX6Q_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA 1006
    +MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 1007
    +MX6Q_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4 1008
    +MX6Q_PAD_GPIO_5__KPP_ROW_7 1009
    +MX6Q_PAD_GPIO_5__CCM_CLKO 1010
    +MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 1011
    +MX6Q_PAD_GPIO_5__GPIO_1_5 1012
    +MX6Q_PAD_GPIO_5__I2C3_SCL 1013
    +MX6Q_PAD_GPIO_5__CHEETAH_EVENTI 1014
    +MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 1015
    +MX6Q_PAD_GPIO_7__ECSPI5_RDY 1016
    +MX6Q_PAD_GPIO_7__EPIT1_EPITO 1017
    +MX6Q_PAD_GPIO_7__CAN1_TXCAN 1018
    +MX6Q_PAD_GPIO_7__UART2_TXD 1019
    +MX6Q_PAD_GPIO_7__GPIO_1_7 1020
    +MX6Q_PAD_GPIO_7__SPDIF_PLOCK 1021
    +MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE 1022
    +MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 1023
    +MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT 1024
    +MX6Q_PAD_GPIO_8__EPIT2_EPITO 1025
    +MX6Q_PAD_GPIO_8__CAN1_RXCAN 1026
    +MX6Q_PAD_GPIO_8__UART2_RXD 1027
    +MX6Q_PAD_GPIO_8__GPIO_1_8 1028
    +MX6Q_PAD_GPIO_8__SPDIF_SRCLK 1029
    +MX6Q_PAD_GPIO_8__USBOH3_OTG_PWRCTL_WAK 1030
    +MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 1031
    +MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN 1032
    +MX6Q_PAD_GPIO_16__ENET_ETHERNET_REF_OUT 1033
    +MX6Q_PAD_GPIO_16__USDHC1_LCTL 1034
    +MX6Q_PAD_GPIO_16__SPDIF_IN1 1035
    +MX6Q_PAD_GPIO_16__GPIO_7_11 1036
    +MX6Q_PAD_GPIO_16__I2C3_SDA 1037
    +MX6Q_PAD_GPIO_16__SJC_DE_B 1038
    +MX6Q_PAD_GPIO_17__ESAI1_TX0 1039
    +MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN 1040
    +MX6Q_PAD_GPIO_17__CCM_PMIC_RDY 1041
    +MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 1042
    +MX6Q_PAD_GPIO_17__SPDIF_OUT1 1043
    +MX6Q_PAD_GPIO_17__GPIO_7_12 1044
    +MX6Q_PAD_GPIO_17__SJC_JTAG_ACT 1045
    +MX6Q_PAD_GPIO_18__ESAI1_TX1 1046
    +MX6Q_PAD_GPIO_18__ENET_RX_CLK 1047
    +MX6Q_PAD_GPIO_18__USDHC3_VSELECT 1048
    +MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 1049
    +MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK 1050
    +MX6Q_PAD_GPIO_18__GPIO_7_13 1051
    +MX6Q_PAD_GPIO_18__SNVS_HP_WRA_SNVS_VIO5 1052
    +MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST 1053
    +MX6Q_PAD_GPIO_19__KPP_COL_5 1054
    +MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT 1055
    +MX6Q_PAD_GPIO_19__SPDIF_OUT1 1056
    +MX6Q_PAD_GPIO_19__CCM_CLKO 1057
    +MX6Q_PAD_GPIO_19__ECSPI1_RDY 1058
    +MX6Q_PAD_GPIO_19__GPIO_4_5 1059
    +MX6Q_PAD_GPIO_19__ENET_TX_ER 1060
    +MX6Q_PAD_GPIO_19__SRC_INT_BOOT 1061
    +MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 1062
    +MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12 1063
    +MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 1064
    +MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 1065
    +MX6Q_PAD_CSI0_PIXCLK___MMDC_DEBUG_29 1066
    +MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO 1067
    +MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 1068
    +MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13 1069
    +MX6Q_PAD_CSI0_MCLK__CCM_CLKO 1070
    +MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 1071
    +MX6Q_PAD_CSI0_MCLK__GPIO_5_19 1072
    +MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 1073
    +MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL 1074
    +MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN 1075
    +MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 1076
    +MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14 1077
    +MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 1078
    +MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 1079
    +MX6Q_PAD_CSI0_DATA_EN__MMDC_DEBUG_31 1080
    +MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK 1081
    +MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 1082
    +MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 1083
    +MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15 1084
    +MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 1085
    +MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 1086
    +MX6Q_PAD_CSI0_VSYNC__MMDC_DEBUG_32 1087
    +MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 1088
    +MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 1089
    +MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 1090
    +MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK 1091
    +MX6Q_PAD_CSI0_DAT4__KPP_COL_5 1092
    +MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 1093
    +MX6Q_PAD_CSI0_DAT4__GPIO_5_22 1094
    +MX6Q_PAD_CSI0_DAT4__MMDC_DEBUG_43 1095
    +MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 1096
    +MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 1097
    +MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 1098
    +MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI 1099
    +MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 1100
    +MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 1101
    +MX6Q_PAD_CSI0_DAT5__GPIO_5_23 1102
    +MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 1103
    +MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 1104
    +MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 1105
    +MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 1106
    +MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO 1107
    +MX6Q_PAD_CSI0_DAT6__KPP_COL_6 1108
    +MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 1109
    +MX6Q_PAD_CSI0_DAT6__GPIO_5_24 1110
    +MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 1111
    +MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 1112
    +MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 1113
    +MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 1114
    +MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 1115
    +MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 1116
    +MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 1117
    +MX6Q_PAD_CSI0_DAT7__GPIO_5_25 1118
    +MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 1119
    +MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 1120
    +MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 1121
    +MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 1122
    +MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK 1123
    +MX6Q_PAD_CSI0_DAT8__KPP_COL_7 1124
    +MX6Q_PAD_CSI0_DAT8__I2C1_SDA 1125
    +MX6Q_PAD_CSI0_DAT8__GPIO_5_26 1126
    +MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 1127
    +MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 1128
    +MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 1129
    +MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 1130
    +MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI 1131
    +MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 1132
    +MX6Q_PAD_CSI0_DAT9__I2C1_SCL 1133
    +MX6Q_PAD_CSI0_DAT9__GPIO_5_27 1134
    +MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 1135
    +MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 1136
    +MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 1137
    +MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC 1138
    +MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO 1139
    +MX6Q_PAD_CSI0_DAT10__UART1_TXD 1140
    +MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 1141
    +MX6Q_PAD_CSI0_DAT10__GPIO_5_28 1142
    +MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 1143
    +MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 1144
    +MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 1145
    +MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS 1146
    +MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 1147
    +MX6Q_PAD_CSI0_DAT11__UART1_RXD 1148
    +MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 1149
    +MX6Q_PAD_CSI0_DAT11__GPIO_5_29 1150
    +MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 1151
    +MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 1152
    +MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 1153
    +MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 1154
    +MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16 1155
    +MX6Q_PAD_CSI0_DAT12__UART4_TXD 1156
    +MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 1157
    +MX6Q_PAD_CSI0_DAT12__GPIO_5_30 1158
    +MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 1159
    +MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 1160
    +MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 1161
    +MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 1162
    +MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17 1163
    +MX6Q_PAD_CSI0_DAT13__UART4_RXD 1164
    +MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 1165
    +MX6Q_PAD_CSI0_DAT13__GPIO_5_31 1166
    +MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 1167
    +MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 1168
    +MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 1169
    +MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 1170
    +MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18 1171
    +MX6Q_PAD_CSI0_DAT14__UART5_TXD 1172
    +MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 1173
    +MX6Q_PAD_CSI0_DAT14__GPIO_6_0 1174
    +MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 1175
    +MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 1176
    +MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 1177
    +MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 1178
    +MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19 1179
    +MX6Q_PAD_CSI0_DAT15__UART5_RXD 1180
    +MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 1181
    +MX6Q_PAD_CSI0_DAT15__GPIO_6_1 1182
    +MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 1183
    +MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 1184
    +MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 1185
    +MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 1186
    +MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20 1187
    +MX6Q_PAD_CSI0_DAT16__UART4_RTS 1188
    +MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 1189
    +MX6Q_PAD_CSI0_DAT16__GPIO_6_2 1190
    +MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 1191
    +MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 1192
    +MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 1193
    +MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 1194
    +MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21 1195
    +MX6Q_PAD_CSI0_DAT17__UART4_CTS 1196
    +MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 1197
    +MX6Q_PAD_CSI0_DAT17__GPIO_6_3 1198
    +MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 1199
    +MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 1200
    +MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 1201
    +MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 1202
    +MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22 1203
    +MX6Q_PAD_CSI0_DAT18__UART5_RTS 1204
    +MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 1205
    +MX6Q_PAD_CSI0_DAT18__GPIO_6_4 1206
    +MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 1207
    +MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 1208
    +MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 1209
    +MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 1210
    +MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23 1211
    +MX6Q_PAD_CSI0_DAT19__UART5_CTS 1212
    +MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 1213
    +MX6Q_PAD_CSI0_DAT19__GPIO_6_5 1214
    +MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 1215
    +MX6Q_PAD_CSI0_DAT19__ANATOP_TESTO_9 1216
    +MX6Q_PAD_JTAG_TMS__SJC_TMS 1217
    +MX6Q_PAD_JTAG_MOD__SJC_MOD 1218
    +MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB 1219
    +MX6Q_PAD_JTAG_TDI__SJC_TDI 1220
    +MX6Q_PAD_JTAG_TCK__SJC_TCK 1221
    +MX6Q_PAD_JTAG_TDO__SJC_TDO 1222
    +MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 1223
    +MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 1224
    +MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 1225
    +MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 1226
    +MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 1227
    +MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 1228
    +MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 1229
    +MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 1230
    +MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 1231
    +MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 1232
    +MX6Q_PAD_TAMPER__SNVS_LP_WRAP_SNVS_TD1 1233
    +MX6Q_PAD_PMIC_ON_REQ__SNVS_LPWRAP_WKALM 1234
    +MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_STBYRQ 1235
    +MX6Q_PAD_POR_B__SRC_POR_B 1236
    +MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 1237
    +MX6Q_PAD_RESET_IN_B__SRC_RESET_B 1238
    +MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 1239
    +MX6Q_PAD_TEST_MODE__TCU_TEST_MODE 1240
    +MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 1241
    +MX6Q_PAD_SD3_DAT7__UART1_TXD 1242
    +MX6Q_PAD_SD3_DAT7__PCIE_CTRL_MUX_24 1243
    +MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 1244
    +MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 1245
    +MX6Q_PAD_SD3_DAT7__GPIO_6_17 1246
    +MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12 1247
    +MX6Q_PAD_SD3_DAT7__USBPHY2_CLK20DIV 1248
    +MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 1249
    +MX6Q_PAD_SD3_DAT6__UART1_RXD 1250
    +MX6Q_PAD_SD3_DAT6__PCIE_CTRL_MUX_25 1251
    +MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 1252
    +MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 1253
    +MX6Q_PAD_SD3_DAT6__GPIO_6_18 1254
    +MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13 1255
    +MX6Q_PAD_SD3_DAT6__ANATOP_TESTO_10 1256
    +MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 1257
    +MX6Q_PAD_SD3_DAT5__UART2_TXD 1258
    +MX6Q_PAD_SD3_DAT5__PCIE_CTRL_MUX_26 1259
    +MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 1260
    +MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 1261
    +MX6Q_PAD_SD3_DAT5__GPIO_7_0 1262
    +MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14 1263
    +MX6Q_PAD_SD3_DAT5__ANATOP_TESTO_11 1264
    +MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 1265
    +MX6Q_PAD_SD3_DAT4__UART2_RXD 1266
    +MX6Q_PAD_SD3_DAT4__PCIE_CTRL_MUX_27 1267
    +MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 1268
    +MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 1269
    +MX6Q_PAD_SD3_DAT4__GPIO_7_1 1270
    +MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15 1271
    +MX6Q_PAD_SD3_DAT4__ANATOP_TESTO_12 1272
    +MX6Q_PAD_SD3_CMD__USDHC3_CMD 1273
    +MX6Q_PAD_SD3_CMD__UART2_CTS 1274
    +MX6Q_PAD_SD3_CMD__CAN1_TXCAN 1275
    +MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 1276
    +MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 1277
    +MX6Q_PAD_SD3_CMD__GPIO_7_2 1278
    +MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16 1279
    +MX6Q_PAD_SD3_CMD__ANATOP_TESTO_13 1280
    +MX6Q_PAD_SD3_CLK__USDHC3_CLK 1281
    +MX6Q_PAD_SD3_CLK__UART2_RTS 1282
    +MX6Q_PAD_SD3_CLK__CAN1_RXCAN 1283
    +MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 1284
    +MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 1285
    +MX6Q_PAD_SD3_CLK__GPIO_7_3 1286
    +MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17 1287
    +MX6Q_PAD_SD3_CLK__ANATOP_TESTO_14 1288
    +MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 1289
    +MX6Q_PAD_SD3_DAT0__UART1_CTS 1290
    +MX6Q_PAD_SD3_DAT0__CAN2_TXCAN 1291
    +MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 1292
    +MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 1293
    +MX6Q_PAD_SD3_DAT0__GPIO_7_4 1294
    +MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18 1295
    +MX6Q_PAD_SD3_DAT0__ANATOP_TESTO_15 1296
    +MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 1297
    +MX6Q_PAD_SD3_DAT1__UART1_RTS 1298
    +MX6Q_PAD_SD3_DAT1__CAN2_RXCAN 1299
    +MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 1300
    +MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 1301
    +MX6Q_PAD_SD3_DAT1__GPIO_7_5 1302
    +MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19 1303
    +MX6Q_PAD_SD3_DAT1__ANATOP_TESTI_0 1304
    +MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 1305
    +MX6Q_PAD_SD3_DAT2__PCIE_CTRL_MUX_28 1306
    +MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 1307
    +MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 1308
    +MX6Q_PAD_SD3_DAT2__GPIO_7_6 1309
    +MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20 1310
    +MX6Q_PAD_SD3_DAT2__ANATOP_TESTI_1 1311
    +MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 1312
    +MX6Q_PAD_SD3_DAT3__UART3_CTS 1313
    +MX6Q_PAD_SD3_DAT3__PCIE_CTRL_MUX_29 1314
    +MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 1315
    +MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 1316
    +MX6Q_PAD_SD3_DAT3__GPIO_7_7 1317
    +MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21 1318
    +MX6Q_PAD_SD3_DAT3__ANATOP_TESTI_2 1319
    +MX6Q_PAD_SD3_RST__USDHC3_RST 1320
    +MX6Q_PAD_SD3_RST__UART3_RTS 1321
    +MX6Q_PAD_SD3_RST__PCIE_CTRL_MUX_30 1322
    +MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 1323
    +MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 1324
    +MX6Q_PAD_SD3_RST__GPIO_7_8 1325
    +MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22 1326
    +MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 1327
    +MX6Q_PAD_NANDF_CLE__RAWNAND_CLE 1328
    +MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 1329
    +MX6Q_PAD_NANDF_CLE__PCIE_CTRL_MUX_31 1330
    +MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11 1331
    +MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11 1332
    +MX6Q_PAD_NANDF_CLE__GPIO_6_7 1333
    +MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23 1334
    +MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 1335
    +MX6Q_PAD_NANDF_ALE__RAWNAND_ALE 1336
    +MX6Q_PAD_NANDF_ALE__USDHC4_RST 1337
    +MX6Q_PAD_NANDF_ALE__PCIE_CTRL_MUX_0 1338
    +MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12 1339
    +MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12 1340
    +MX6Q_PAD_NANDF_ALE__GPIO_6_8 1341
    +MX6Q_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24 1342
    +MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 1343
    +MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN 1344
    +MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 1345
    +MX6Q_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1 1346
    +MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13 1347
    +MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13 1348
    +MX6Q_PAD_NANDF_WP_B__GPIO_6_9 1349
    +MX6Q_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32 1350
    +MX6Q_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0 1351
    +MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 1352
    +MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 1353
    +MX6Q_PAD_NANDF_RB0__PCIE_CTRL_MUX_2 1354
    +MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14 1355
    +MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14 1356
    +MX6Q_PAD_NANDF_RB0__GPIO_6_10 1357
    +MX6Q_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33 1358
    +MX6Q_PAD_NANDF_RB0__PL301_PER1_HSIZE_1 1359
    +MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N 1360
    +MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OT15 1361
    +MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OT15 1362
    +MX6Q_PAD_NANDF_CS0__GPIO_6_11 1363
    +MX6Q_PAD_NANDF_CS0__PL301_PER1_HSIZE_2 1364
    +MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N 1365
    +MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT 1366
    +MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT 1367
    +MX6Q_PAD_NANDF_CS1__PCIE_CTRL_MUX_3 1368
    +MX6Q_PAD_NANDF_CS1__GPIO_6_14 1369
    +MX6Q_PAD_NANDF_CS1__PL301_PER1_HRDYOUT 1370
    +MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N 1371
    +MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 1372
    +MX6Q_PAD_NANDF_CS2__ESAI1_TX0 1373
    +MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE 1374
    +MX6Q_PAD_NANDF_CS2__CCM_CLKO2 1375
    +MX6Q_PAD_NANDF_CS2__GPIO_6_15 1376
    +MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 1377
    +MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N 1378
    +MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 1379
    +MX6Q_PAD_NANDF_CS3__ESAI1_TX1 1380
    +MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 1381
    +MX6Q_PAD_NANDF_CS3__PCIE_CTRL_MUX_4 1382
    +MX6Q_PAD_NANDF_CS3__GPIO_6_16 1383
    +MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 1384
    +MX6Q_PAD_NANDF_CS3__TPSMP_CLK 1385
    +MX6Q_PAD_SD4_CMD__USDHC4_CMD 1386
    +MX6Q_PAD_SD4_CMD__RAWNAND_RDN 1387
    +MX6Q_PAD_SD4_CMD__UART3_TXD 1388
    +MX6Q_PAD_SD4_CMD__PCIE_CTRL_MUX_5 1389
    +MX6Q_PAD_SD4_CMD__GPIO_7_9 1390
    +MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR 1391
    +MX6Q_PAD_SD4_CLK__USDHC4_CLK 1392
    +MX6Q_PAD_SD4_CLK__RAWNAND_WRN 1393
    +MX6Q_PAD_SD4_CLK__UART3_RXD 1394
    +MX6Q_PAD_SD4_CLK__PCIE_CTRL_MUX_6 1395
    +MX6Q_PAD_SD4_CLK__GPIO_7_10 1396
    +MX6Q_PAD_NANDF_D0__RAWNAND_D0 1397
    +MX6Q_PAD_NANDF_D0__USDHC1_DAT4 1398
    +MX6Q_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0 1399
    +MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT16 1400
    +MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT16 1401
    +MX6Q_PAD_NANDF_D0__GPIO_2_0 1402
    +MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 1403
    +MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 1404
    +MX6Q_PAD_NANDF_D1__RAWNAND_D1 1405
    +MX6Q_PAD_NANDF_D1__USDHC1_DAT5 1406
    +MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1 1407
    +MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT17 1408
    +MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT17 1409
    +MX6Q_PAD_NANDF_D1__GPIO_2_1 1410
    +MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 1411
    +MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 1412
    +MX6Q_PAD_NANDF_D2__RAWNAND_D2 1413
    +MX6Q_PAD_NANDF_D2__USDHC1_DAT6 1414
    +MX6Q_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2 1415
    +MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT18 1416
    +MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT18 1417
    +MX6Q_PAD_NANDF_D2__GPIO_2_2 1418
    +MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 1419
    +MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 1420
    +MX6Q_PAD_NANDF_D3__RAWNAND_D3 1421
    +MX6Q_PAD_NANDF_D3__USDHC1_DAT7 1422
    +MX6Q_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3 1423
    +MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT19 1424
    +MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT19 1425
    +MX6Q_PAD_NANDF_D3__GPIO_2_3 1426
    +MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 1427
    +MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 1428
    +MX6Q_PAD_NANDF_D4__RAWNAND_D4 1429
    +MX6Q_PAD_NANDF_D4__USDHC2_DAT4 1430
    +MX6Q_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4 1431
    +MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT20 1432
    +MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT20 1433
    +MX6Q_PAD_NANDF_D4__GPIO_2_4 1434
    +MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 1435
    +MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 1436
    +MX6Q_PAD_NANDF_D5__RAWNAND_D5 1437
    +MX6Q_PAD_NANDF_D5__USDHC2_DAT5 1438
    +MX6Q_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5 1439
    +MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT21 1440
    +MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT21 1441
    +MX6Q_PAD_NANDF_D5__GPIO_2_5 1442
    +MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 1443
    +MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 1444
    +MX6Q_PAD_NANDF_D6__RAWNAND_D6 1445
    +MX6Q_PAD_NANDF_D6__USDHC2_DAT6 1446
    +MX6Q_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6 1447
    +MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT22 1448
    +MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT22 1449
    +MX6Q_PAD_NANDF_D6__GPIO_2_6 1450
    +MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 1451
    +MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 1452
    +MX6Q_PAD_NANDF_D7__RAWNAND_D7 1453
    +MX6Q_PAD_NANDF_D7__USDHC2_DAT7 1454
    +MX6Q_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7 1455
    +MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT23 1456
    +MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT23 1457
    +MX6Q_PAD_NANDF_D7__GPIO_2_7 1458
    +MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 1459
    +MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 1460
    +MX6Q_PAD_SD4_DAT0__RAWNAND_D8 1461
    +MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 1462
    +MX6Q_PAD_SD4_DAT0__RAWNAND_DQS 1463
    +MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT24 1464
    +MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT24 1465
    +MX6Q_PAD_SD4_DAT0__GPIO_2_8 1466
    +MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 1467
    +MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 1468
    +MX6Q_PAD_SD4_DAT1__RAWNAND_D9 1469
    +MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 1470
    +MX6Q_PAD_SD4_DAT1__PWM3_PWMO 1471
    +MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT25 1472
    +MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT25 1473
    +MX6Q_PAD_SD4_DAT1__GPIO_2_9 1474
    +MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 1475
    +MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 1476
    +MX6Q_PAD_SD4_DAT2__RAWNAND_D10 1477
    +MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 1478
    +MX6Q_PAD_SD4_DAT2__PWM4_PWMO 1479
    +MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT26 1480
    +MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT26 1481
    +MX6Q_PAD_SD4_DAT2__GPIO_2_10 1482
    +MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 1483
    +MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 1484
    +MX6Q_PAD_SD4_DAT3__RAWNAND_D11 1485
    +MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 1486
    +MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT27 1487
    +MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT27 1488
    +MX6Q_PAD_SD4_DAT3__GPIO_2_11 1489
    +MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 1490
    +MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 1491
    +MX6Q_PAD_SD4_DAT4__RAWNAND_D12 1492
    +MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 1493
    +MX6Q_PAD_SD4_DAT4__UART2_RXD 1494
    +MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28 1495
    +MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28 1496
    +MX6Q_PAD_SD4_DAT4__GPIO_2_12 1497
    +MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 1498
    +MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 1499
    +MX6Q_PAD_SD4_DAT5__RAWNAND_D13 1500
    +MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 1501
    +MX6Q_PAD_SD4_DAT5__UART2_RTS 1502
    +MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29 1503
    +MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29 1504
    +MX6Q_PAD_SD4_DAT5__GPIO_2_13 1505
    +MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 1506
    +MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 1507
    +MX6Q_PAD_SD4_DAT6__RAWNAND_D14 1508
    +MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 1509
    +MX6Q_PAD_SD4_DAT6__UART2_CTS 1510
    +MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30 1511
    +MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30 1512
    +MX6Q_PAD_SD4_DAT6__GPIO_2_14 1513
    +MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 1514
    +MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 1515
    +MX6Q_PAD_SD4_DAT7__RAWNAND_D15 1516
    +MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 1517
    +MX6Q_PAD_SD4_DAT7__UART2_TXD 1518
    +MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31 1519
    +MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31 1520
    +MX6Q_PAD_SD4_DAT7__GPIO_2_15 1521
    +MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 1522
    +MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 1523
    +MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 1524
    +MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 1525
    +MX6Q_PAD_SD1_DAT1__PWM3_PWMO 1526
    +MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 1527
    +MX6Q_PAD_SD1_DAT1__PCIE_CTRL_MUX_7 1528
    +MX6Q_PAD_SD1_DAT1__GPIO_1_17 1529
    +MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 1530
    +MX6Q_PAD_SD1_DAT1__ANATOP_TESTO_8 1531
    +MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 1532
    +MX6Q_PAD_SD1_DAT0__ECSPI5_MISO 1533
    +MX6Q_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS 1534
    +MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 1535
    +MX6Q_PAD_SD1_DAT0__PCIE_CTRL_MUX_8 1536
    +MX6Q_PAD_SD1_DAT0__GPIO_1_16 1537
    +MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 1538
    +MX6Q_PAD_SD1_DAT0__ANATOP_TESTO_7 1539
    +MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 1540
    +MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 1541
    +MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 1542
    +MX6Q_PAD_SD1_DAT3__PWM1_PWMO 1543
    +MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B 1544
    +MX6Q_PAD_SD1_DAT3__GPIO_1_21 1545
    +MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB 1546
    +MX6Q_PAD_SD1_DAT3__ANATOP_TESTO_6 1547
    +MX6Q_PAD_SD1_CMD__USDHC1_CMD 1548
    +MX6Q_PAD_SD1_CMD__ECSPI5_MOSI 1549
    +MX6Q_PAD_SD1_CMD__PWM4_PWMO 1550
    +MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 1551
    +MX6Q_PAD_SD1_CMD__GPIO_1_18 1552
    +MX6Q_PAD_SD1_CMD__ANATOP_TESTO_5 1553
    +MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 1554
    +MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 1555
    +MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 1556
    +MX6Q_PAD_SD1_DAT2__PWM2_PWMO 1557
    +MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B 1558
    +MX6Q_PAD_SD1_DAT2__GPIO_1_19 1559
    +MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB 1560
    +MX6Q_PAD_SD1_DAT2__ANATOP_TESTO_4 1561
    +MX6Q_PAD_SD1_CLK__USDHC1_CLK 1562
    +MX6Q_PAD_SD1_CLK__ECSPI5_SCLK 1563
    +MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT 1564
    +MX6Q_PAD_SD1_CLK__GPT_CLKIN 1565
    +MX6Q_PAD_SD1_CLK__GPIO_1_20 1566
    +MX6Q_PAD_SD1_CLK__PHY_DTB_0 1567
    +MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 1568
    +MX6Q_PAD_SD2_CLK__USDHC2_CLK 1569
    +MX6Q_PAD_SD2_CLK__ECSPI5_SCLK 1570
    +MX6Q_PAD_SD2_CLK__KPP_COL_5 1571
    +MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS 1572
    +MX6Q_PAD_SD2_CLK__PCIE_CTRL_MUX_9 1573
    +MX6Q_PAD_SD2_CLK__GPIO_1_10 1574
    +MX6Q_PAD_SD2_CLK__PHY_DTB_1 1575
    +MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 1576
    +MX6Q_PAD_SD2_CMD__USDHC2_CMD 1577
    +MX6Q_PAD_SD2_CMD__ECSPI5_MOSI 1578
    +MX6Q_PAD_SD2_CMD__KPP_ROW_5 1579
    +MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC 1580
    +MX6Q_PAD_SD2_CMD__PCIE_CTRL_MUX_10 1581
    +MX6Q_PAD_SD2_CMD__GPIO_1_11 1582
    +MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 1583
    +MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 1584
    +MX6Q_PAD_SD2_DAT3__KPP_COL_6 1585
    +MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC 1586
    +MX6Q_PAD_SD2_DAT3__PCIE_CTRL_MUX_11 1587
    +MX6Q_PAD_SD2_DAT3__GPIO_1_12 1588
    +MX6Q_PAD_SD2_DAT3__SJC_DONE 1589
    +MX6Q_PAD_SD2_DAT3__ANATOP_TESTO_3 1590
    diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
    index aad2882..40d78aa 100644
    --- a/drivers/pinctrl/Kconfig
    +++ b/drivers/pinctrl/Kconfig
    @@ -31,6 +31,14 @@ config PINCTRL_IMX
    select PINMUX
    select PINCONF

    +config PINCTRL_IMX6Q
    + bool "IMX6Q pinctrl driver"
    + depends on OF
    + depends on SOC_IMX6Q
    + select PINCTRL_IMX
    + help
    + Say Y here to enable the imx6q pinctrl driver
    +
    config PINCTRL_PXA3xx
    bool
    select PINMUX
    diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
    index a01a97c..133261d 100644
    --- a/drivers/pinctrl/Makefile
    +++ b/drivers/pinctrl/Makefile
    @@ -10,6 +10,7 @@ obj-$(CONFIG_PINCTRL) += devicetree.o
    endif
    obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o
    obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
    +obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
    obj-$(CONFIG_PINCTRL_PXA3xx) += pinctrl-pxa3xx.o
    obj-$(CONFIG_PINCTRL_MMP2) += pinctrl-mmp2.o
    obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o
    diff --git a/drivers/pinctrl/pinctrl-imx6q.c b/drivers/pinctrl/pinctrl-imx6q.c
    new file mode 100644
    index 0000000..7737d4d
    --- /dev/null
    +++ b/drivers/pinctrl/pinctrl-imx6q.c
    @@ -0,0 +1,2331 @@
    +/*
    + * imx6q pinctrl driver based on imx pinmux core
    + *
    + * Copyright (C) 2012 Freescale Semiconductor, Inc.
    + * Copyright (C) 2012 Linaro, Inc.
    + *
    + * Author: Dong Aisheng <dong.aisheng@linaro.org>
    + *
    + * This program is free software; you can redistribute it and/or modify
    + * it under the terms of the GNU General Public License as published by
    + * the Free Software Foundation; either version 2 of the License, or
    + * (at your option) any later version.
    + */
    +
    +#include <linux/err.h>
    +#include <linux/init.h>
    +#include <linux/io.h>
    +#include <linux/module.h>
    +#include <linux/of.h>
    +#include <linux/of_device.h>
    +#include <linux/pinctrl/pinctrl.h>
    +
    +#include "pinctrl-imx.h"
    +
    +enum imx6q_pads {
    + MX6Q_PAD_SD2_DAT1 = 0,
    + MX6Q_PAD_SD2_DAT2 = 1,
    + MX6Q_PAD_SD2_DAT0 = 2,
    + MX6Q_PAD_RGMII_TXC = 3,
    + MX6Q_PAD_RGMII_TD0 = 4,
    + MX6Q_PAD_RGMII_TD1 = 5,
    + MX6Q_PAD_RGMII_TD2 = 6,
    + MX6Q_PAD_RGMII_TD3 = 7,
    + MX6Q_PAD_RGMII_RX_CTL = 8,
    + MX6Q_PAD_RGMII_RD0 = 9,
    + MX6Q_PAD_RGMII_TX_CTL = 10,
    + MX6Q_PAD_RGMII_RD1 = 11,
    + MX6Q_PAD_RGMII_RD2 = 12,
    + MX6Q_PAD_RGMII_RD3 = 13,
    + MX6Q_PAD_RGMII_RXC = 14,
    + MX6Q_PAD_EIM_A25 = 15,
    + MX6Q_PAD_EIM_EB2 = 16,
    + MX6Q_PAD_EIM_D16 = 17,
    + MX6Q_PAD_EIM_D17 = 18,
    + MX6Q_PAD_EIM_D18 = 19,
    + MX6Q_PAD_EIM_D19 = 20,
    + MX6Q_PAD_EIM_D20 = 21,
    + MX6Q_PAD_EIM_D21 = 22,
    + MX6Q_PAD_EIM_D22 = 23,
    + MX6Q_PAD_EIM_D23 = 24,
    + MX6Q_PAD_EIM_EB3 = 25,
    + MX6Q_PAD_EIM_D24 = 26,
    + MX6Q_PAD_EIM_D25 = 27,
    + MX6Q_PAD_EIM_D26 = 28,
    + MX6Q_PAD_EIM_D27 = 29,
    + MX6Q_PAD_EIM_D28 = 30,
    + MX6Q_PAD_EIM_D29 = 31,
    + MX6Q_PAD_EIM_D30 = 32,
    + MX6Q_PAD_EIM_D31 = 33,
    + MX6Q_PAD_EIM_A24 = 34,
    + MX6Q_PAD_EIM_A23 = 35,
    + MX6Q_PAD_EIM_A22 = 36,
    + MX6Q_PAD_EIM_A21 = 37,
    + MX6Q_PAD_EIM_A20 = 38,
    + MX6Q_PAD_EIM_A19 = 39,
    + MX6Q_PAD_EIM_A18 = 40,
    + MX6Q_PAD_EIM_A17 = 41,
    + MX6Q_PAD_EIM_A16 = 42,
    + MX6Q_PAD_EIM_CS0 = 43,
    + MX6Q_PAD_EIM_CS1 = 44,
    + MX6Q_PAD_EIM_OE = 45,
    + MX6Q_PAD_EIM_RW = 46,
    + MX6Q_PAD_EIM_LBA = 47,
    + MX6Q_PAD_EIM_EB0 = 48,
    + MX6Q_PAD_EIM_EB1 = 49,
    + MX6Q_PAD_EIM_DA0 = 50,
    + MX6Q_PAD_EIM_DA1 = 51,
    + MX6Q_PAD_EIM_DA2 = 52,
    + MX6Q_PAD_EIM_DA3 = 53,
    + MX6Q_PAD_EIM_DA4 = 54,
    + MX6Q_PAD_EIM_DA5 = 55,
    + MX6Q_PAD_EIM_DA6 = 56,
    + MX6Q_PAD_EIM_DA7 = 57,
    + MX6Q_PAD_EIM_DA8 = 58,
    + MX6Q_PAD_EIM_DA9 = 59,
    + MX6Q_PAD_EIM_DA10 = 60,
    + MX6Q_PAD_EIM_DA11 = 61,
    + MX6Q_PAD_EIM_DA12 = 62,
    + MX6Q_PAD_EIM_DA13 = 63,
    + MX6Q_PAD_EIM_DA14 = 64,
    + MX6Q_PAD_EIM_DA15 = 65,
    + MX6Q_PAD_EIM_WAIT = 66,
    + MX6Q_PAD_EIM_BCLK = 67,
    + MX6Q_PAD_DI0_DISP_CLK = 68,
    + MX6Q_PAD_DI0_PIN15 = 69,
    + MX6Q_PAD_DI0_PIN2 = 70,
    + MX6Q_PAD_DI0_PIN3 = 71,
    + MX6Q_PAD_DI0_PIN4 = 72,
    + MX6Q_PAD_DISP0_DAT0 = 73,
    + MX6Q_PAD_DISP0_DAT1 = 74,
    + MX6Q_PAD_DISP0_DAT2 = 75,
    + MX6Q_PAD_DISP0_DAT3 = 76,
    + MX6Q_PAD_DISP0_DAT4 = 77,
    + MX6Q_PAD_DISP0_DAT5 = 78,
    + MX6Q_PAD_DISP0_DAT6 = 79,
    + MX6Q_PAD_DISP0_DAT7 = 80,
    + MX6Q_PAD_DISP0_DAT8 = 81,
    + MX6Q_PAD_DISP0_DAT9 = 82,
    + MX6Q_PAD_DISP0_DAT10 = 83,
    + MX6Q_PAD_DISP0_DAT11 = 84,
    + MX6Q_PAD_DISP0_DAT12 = 85,
    + MX6Q_PAD_DISP0_DAT13 = 86,
    + MX6Q_PAD_DISP0_DAT14 = 87,
    + MX6Q_PAD_DISP0_DAT15 = 88,
    + MX6Q_PAD_DISP0_DAT16 = 89,
    + MX6Q_PAD_DISP0_DAT17 = 90,
    + MX6Q_PAD_DISP0_DAT18 = 91,
    + MX6Q_PAD_DISP0_DAT19 = 92,
    + MX6Q_PAD_DISP0_DAT20 = 93,
    + MX6Q_PAD_DISP0_DAT21 = 94,
    + MX6Q_PAD_DISP0_DAT22 = 95,
    + MX6Q_PAD_DISP0_DAT23 = 96,
    + MX6Q_PAD_ENET_MDIO = 97,
    + MX6Q_PAD_ENET_REF_CLK = 98,
    + MX6Q_PAD_ENET_RX_ER = 99,
    + MX6Q_PAD_ENET_CRS_DV = 100,
    + MX6Q_PAD_ENET_RXD1 = 101,
    + MX6Q_PAD_ENET_RXD0 = 102,
    + MX6Q_PAD_ENET_TX_EN = 103,
    + MX6Q_PAD_ENET_TXD1 = 104,
    + MX6Q_PAD_ENET_TXD0 = 105,
    + MX6Q_PAD_ENET_MDC = 106,
    + MX6Q_PAD_DRAM_D40 = 107,
    + MX6Q_PAD_DRAM_D41 = 108,
    + MX6Q_PAD_DRAM_D42 = 109,
    + MX6Q_PAD_DRAM_D43 = 110,
    + MX6Q_PAD_DRAM_D44 = 111,
    + MX6Q_PAD_DRAM_D45 = 112,
    + MX6Q_PAD_DRAM_D46 = 113,
    + MX6Q_PAD_DRAM_D47 = 114,
    + MX6Q_PAD_DRAM_SDQS5 = 115,
    + MX6Q_PAD_DRAM_DQM5 = 116,
    + MX6Q_PAD_DRAM_D32 = 117,
    + MX6Q_PAD_DRAM_D33 = 118,
    + MX6Q_PAD_DRAM_D34 = 119,
    + MX6Q_PAD_DRAM_D35 = 120,
    + MX6Q_PAD_DRAM_D36 = 121,
    + MX6Q_PAD_DRAM_D37 = 122,
    + MX6Q_PAD_DRAM_D38 = 123,
    + MX6Q_PAD_DRAM_D39 = 124,
    + MX6Q_PAD_DRAM_DQM4 = 125,
    + MX6Q_PAD_DRAM_SDQS4 = 126,
    + MX6Q_PAD_DRAM_D24 = 127,
    + MX6Q_PAD_DRAM_D25 = 128,
    + MX6Q_PAD_DRAM_D26 = 129,
    + MX6Q_PAD_DRAM_D27 = 130,
    + MX6Q_PAD_DRAM_D28 = 131,
    + MX6Q_PAD_DRAM_D29 = 132,
    + MX6Q_PAD_DRAM_SDQS3 = 133,
    + MX6Q_PAD_DRAM_D30 = 134,
    + MX6Q_PAD_DRAM_D31 = 135,
    + MX6Q_PAD_DRAM_DQM3 = 136,
    + MX6Q_PAD_DRAM_D16 = 137,
    + MX6Q_PAD_DRAM_D17 = 138,
    + MX6Q_PAD_DRAM_D18 = 139,
    + MX6Q_PAD_DRAM_D19 = 140,
    + MX6Q_PAD_DRAM_D20 = 141,
    + MX6Q_PAD_DRAM_D21 = 142,
    + MX6Q_PAD_DRAM_D22 = 143,
    + MX6Q_PAD_DRAM_SDQS2 = 144,
    + MX6Q_PAD_DRAM_D23 = 145,
    + MX6Q_PAD_DRAM_DQM2 = 146,
    + MX6Q_PAD_DRAM_A0 = 147,
    + MX6Q_PAD_DRAM_A1 = 148,
    + MX6Q_PAD_DRAM_A2 = 149,
    + MX6Q_PAD_DRAM_A3 = 150,
    + MX6Q_PAD_DRAM_A4 = 151,
    + MX6Q_PAD_DRAM_A5 = 152,
    + MX6Q_PAD_DRAM_A6 = 153,
    + MX6Q_PAD_DRAM_A7 = 154,
    + MX6Q_PAD_DRAM_A8 = 155,
    + MX6Q_PAD_DRAM_A9 = 156,
    + MX6Q_PAD_DRAM_A10 = 157,
    + MX6Q_PAD_DRAM_A11 = 158,
    + MX6Q_PAD_DRAM_A12 = 159,
    + MX6Q_PAD_DRAM_A13 = 160,
    + MX6Q_PAD_DRAM_A14 = 161,
    + MX6Q_PAD_DRAM_A15 = 162,
    + MX6Q_PAD_DRAM_CAS = 163,
    + MX6Q_PAD_DRAM_CS0 = 164,
    + MX6Q_PAD_DRAM_CS1 = 165,
    + MX6Q_PAD_DRAM_RAS = 166,
    + MX6Q_PAD_DRAM_RESET = 167,
    + MX6Q_PAD_DRAM_SDBA0 = 168,
    + MX6Q_PAD_DRAM_SDBA1 = 169,
    + MX6Q_PAD_DRAM_SDCLK_0 = 170,
    + MX6Q_PAD_DRAM_SDBA2 = 171,
    + MX6Q_PAD_DRAM_SDCKE0 = 172,
    + MX6Q_PAD_DRAM_SDCLK_1 = 173,
    + MX6Q_PAD_DRAM_SDCKE1 = 174,
    + MX6Q_PAD_DRAM_SDODT0 = 175,
    + MX6Q_PAD_DRAM_SDODT1 = 176,
    + MX6Q_PAD_DRAM_SDWE = 177,
    + MX6Q_PAD_DRAM_D0 = 178,
    + MX6Q_PAD_DRAM_D1 = 179,
    + MX6Q_PAD_DRAM_D2 = 180,
    + MX6Q_PAD_DRAM_D3 = 181,
    + MX6Q_PAD_DRAM_D4 = 182,
    + MX6Q_PAD_DRAM_D5 = 183,
    + MX6Q_PAD_DRAM_SDQS0 = 184,
    + MX6Q_PAD_DRAM_D6 = 185,
    + MX6Q_PAD_DRAM_D7 = 186,
    + MX6Q_PAD_DRAM_DQM0 = 187,
    + MX6Q_PAD_DRAM_D8 = 188,
    + MX6Q_PAD_DRAM_D9 = 189,
    + MX6Q_PAD_DRAM_D10 = 190,
    + MX6Q_PAD_DRAM_D11 = 191,
    + MX6Q_PAD_DRAM_D12 = 192,
    + MX6Q_PAD_DRAM_D13 = 193,
    + MX6Q_PAD_DRAM_D14 = 194,
    + MX6Q_PAD_DRAM_SDQS1 = 195,
    + MX6Q_PAD_DRAM_D15 = 196,
    + MX6Q_PAD_DRAM_DQM1 = 197,
    + MX6Q_PAD_DRAM_D48 = 198,
    + MX6Q_PAD_DRAM_D49 = 199,
    + MX6Q_PAD_DRAM_D50 = 200,
    + MX6Q_PAD_DRAM_D51 = 201,
    + MX6Q_PAD_DRAM_D52 = 202,
    + MX6Q_PAD_DRAM_D53 = 203,
    + MX6Q_PAD_DRAM_D54 = 204,
    + MX6Q_PAD_DRAM_D55 = 205,
    + MX6Q_PAD_DRAM_SDQS6 = 206,
    + MX6Q_PAD_DRAM_DQM6 = 207,
    + MX6Q_PAD_DRAM_D56 = 208,
    + MX6Q_PAD_DRAM_SDQS7 = 209,
    + MX6Q_PAD_DRAM_D57 = 210,
    + MX6Q_PAD_DRAM_D58 = 211,
    + MX6Q_PAD_DRAM_D59 = 212,
    + MX6Q_PAD_DRAM_D60 = 213,
    + MX6Q_PAD_DRAM_DQM7 = 214,
    + MX6Q_PAD_DRAM_D61 = 215,
    + MX6Q_PAD_DRAM_D62 = 216,
    + MX6Q_PAD_DRAM_D63 = 217,
    + MX6Q_PAD_KEY_COL0 = 218,
    + MX6Q_PAD_KEY_ROW0 = 219,
    + MX6Q_PAD_KEY_COL1 = 220,
    + MX6Q_PAD_KEY_ROW1 = 221,
    + MX6Q_PAD_KEY_COL2 = 222,
    + MX6Q_PAD_KEY_ROW2 = 223,
    + MX6Q_PAD_KEY_COL3 = 224,
    + MX6Q_PAD_KEY_ROW3 = 225,
    + MX6Q_PAD_KEY_COL4 = 226,
    + MX6Q_PAD_KEY_ROW4 = 227,
    + MX6Q_PAD_GPIO_0 = 228,
    + MX6Q_PAD_GPIO_1 = 229,
    + MX6Q_PAD_GPIO_9 = 230,
    + MX6Q_PAD_GPIO_3 = 231,
    + MX6Q_PAD_GPIO_6 = 232,
    + MX6Q_PAD_GPIO_2 = 233,
    + MX6Q_PAD_GPIO_4 = 234,
    + MX6Q_PAD_GPIO_5 = 235,
    + MX6Q_PAD_GPIO_7 = 236,
    + MX6Q_PAD_GPIO_8 = 237,
    + MX6Q_PAD_GPIO_16 = 238,
    + MX6Q_PAD_GPIO_17 = 239,
    + MX6Q_PAD_GPIO_18 = 240,
    + MX6Q_PAD_GPIO_19 = 241,
    + MX6Q_PAD_CSI0_PIXCLK = 242,
    + MX6Q_PAD_CSI0_MCLK = 243,
    + MX6Q_PAD_CSI0_DATA_EN = 244,
    + MX6Q_PAD_CSI0_VSYNC = 245,
    + MX6Q_PAD_CSI0_DAT4 = 246,
    + MX6Q_PAD_CSI0_DAT5 = 247,
    + MX6Q_PAD_CSI0_DAT6 = 248,
    + MX6Q_PAD_CSI0_DAT7 = 249,
    + MX6Q_PAD_CSI0_DAT8 = 250,
    + MX6Q_PAD_CSI0_DAT9 = 251,
    + MX6Q_PAD_CSI0_DAT10 = 252,
    + MX6Q_PAD_CSI0_DAT11 = 253,
    + MX6Q_PAD_CSI0_DAT12 = 254,
    + MX6Q_PAD_CSI0_DAT13 = 255,
    + MX6Q_PAD_CSI0_DAT14 = 256,
    + MX6Q_PAD_CSI0_DAT15 = 257,
    + MX6Q_PAD_CSI0_DAT16 = 258,
    + MX6Q_PAD_CSI0_DAT17 = 259,
    + MX6Q_PAD_CSI0_DAT18 = 260,
    + MX6Q_PAD_CSI0_DAT19 = 261,
    + MX6Q_PAD_JTAG_TMS = 262,
    + MX6Q_PAD_JTAG_MOD = 263,
    + MX6Q_PAD_JTAG_TRSTB = 264,
    + MX6Q_PAD_JTAG_TDI = 265,
    + MX6Q_PAD_JTAG_TCK = 266,
    + MX6Q_PAD_JTAG_TDO = 267,
    + MX6Q_PAD_LVDS1_TX3_P = 268,
    + MX6Q_PAD_LVDS1_TX2_P = 269,
    + MX6Q_PAD_LVDS1_CLK_P = 270,
    + MX6Q_PAD_LVDS1_TX1_P = 271,
    + MX6Q_PAD_LVDS1_TX0_P = 272,
    + MX6Q_PAD_LVDS0_TX3_P = 273,
    + MX6Q_PAD_LVDS0_CLK_P = 274,
    + MX6Q_PAD_LVDS0_TX2_P = 275,
    + MX6Q_PAD_LVDS0_TX1_P = 276,
    + MX6Q_PAD_LVDS0_TX0_P = 277,
    + MX6Q_PAD_TAMPER = 278,
    + MX6Q_PAD_PMIC_ON_REQ = 279,
    + MX6Q_PAD_PMIC_STBY_REQ = 280,
    + MX6Q_PAD_POR_B = 281,
    + MX6Q_PAD_BOOT_MODE1 = 282,
    + MX6Q_PAD_RESET_IN_B = 283,
    + MX6Q_PAD_BOOT_MODE0 = 284,
    + MX6Q_PAD_TEST_MODE = 285,
    + MX6Q_PAD_SD3_DAT7 = 286,
    + MX6Q_PAD_SD3_DAT6 = 287,
    + MX6Q_PAD_SD3_DAT5 = 288,
    + MX6Q_PAD_SD3_DAT4 = 289,
    + MX6Q_PAD_SD3_CMD = 290,
    + MX6Q_PAD_SD3_CLK = 291,
    + MX6Q_PAD_SD3_DAT0 = 292,
    + MX6Q_PAD_SD3_DAT1 = 293,
    + MX6Q_PAD_SD3_DAT2 = 294,
    + MX6Q_PAD_SD3_DAT3 = 295,
    + MX6Q_PAD_SD3_RST = 296,
    + MX6Q_PAD_NANDF_CLE = 297,
    + MX6Q_PAD_NANDF_ALE = 298,
    + MX6Q_PAD_NANDF_WP_B = 299,
    + MX6Q_PAD_NANDF_RB0 = 300,
    + MX6Q_PAD_NANDF_CS0 = 301,
    + MX6Q_PAD_NANDF_CS1 = 302,
    + MX6Q_PAD_NANDF_CS2 = 303,
    + MX6Q_PAD_NANDF_CS3 = 304,
    + MX6Q_PAD_SD4_CMD = 305,
    + MX6Q_PAD_SD4_CLK = 306,
    + MX6Q_PAD_NANDF_D0 = 307,
    + MX6Q_PAD_NANDF_D1 = 308,
    + MX6Q_PAD_NANDF_D2 = 309,
    + MX6Q_PAD_NANDF_D3 = 310,
    + MX6Q_PAD_NANDF_D4 = 311,
    + MX6Q_PAD_NANDF_D5 = 312,
    + MX6Q_PAD_NANDF_D6 = 313,
    + MX6Q_PAD_NANDF_D7 = 314,
    + MX6Q_PAD_SD4_DAT0 = 315,
    + MX6Q_PAD_SD4_DAT1 = 316,
    + MX6Q_PAD_SD4_DAT2 = 317,
    + MX6Q_PAD_SD4_DAT3 = 318,
    + MX6Q_PAD_SD4_DAT4 = 319,
    + MX6Q_PAD_SD4_DAT5 = 320,
    + MX6Q_PAD_SD4_DAT6 = 321,
    + MX6Q_PAD_SD4_DAT7 = 322,
    + MX6Q_PAD_SD1_DAT1 = 323,
    + MX6Q_PAD_SD1_DAT0 = 324,
    + MX6Q_PAD_SD1_DAT3 = 325,
    + MX6Q_PAD_SD1_CMD = 326,
    + MX6Q_PAD_SD1_DAT2 = 327,
    + MX6Q_PAD_SD1_CLK = 328,
    + MX6Q_PAD_SD2_CLK = 329,
    + MX6Q_PAD_SD2_CMD = 330,
    + MX6Q_PAD_SD2_DAT3 = 331,
    +};
    +
    +/* imx6q register maps */
    +static struct imx_pin_reg imx6q_pin_regs[] = {
    + IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
    + IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 1, 0x0834, 0), /* MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 */
    + IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 2, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 */
    + IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 3, 0x07C8, 0), /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
    + IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 4, 0x08F0, 0), /* MX6Q_PAD_SD2_DAT1__KPP_COL_7 */
    + IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__GPIO_1_14 */
    + IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__CCM_WAIT */
    + IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__ANATOP_TESTO_0 */
    + IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
    + IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 1, 0x0838, 0), /* MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 */
    + IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 2, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 */
    + IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 3, 0x07B8, 0), /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
    + IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 4, 0x08F8, 0), /* MX6Q_PAD_SD2_DAT2__KPP_ROW_6 */
    + IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__GPIO_1_13 */
    + IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__CCM_STOP */
    + IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__ANATOP_TESTO_1 */
    + IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
    + IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 1, 0x082C, 0), /* MX6Q_PAD_SD2_DAT0__ECSPI5_MISO */
    + IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 3, 0x07B4, 0), /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
    + IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 4, 0x08FC, 0), /* MX6Q_PAD_SD2_DAT0__KPP_ROW_7 */
    + IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__GPIO_1_15 */
    + IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT */
    + IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__TESTO_2 */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 2, 0x0918, 0), /* MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__GPIO_6_19 */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0 */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__ANATOP_24M_OUT */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__GPIO_6_20 */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1 */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__GPIO_6_21 */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2 */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__GPIO_6_22 */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3 */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__GPIO_6_23 */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4 */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 1, 0x0858, 0), /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5 */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 1, 0x0848, 0), /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD0__GPIO_6_25 */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6 */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7 */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 7, 0x083C, 0), /* MX6Q_PAD_RGMII_TX_CTL__ANATOP_REF_OUT */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 1, 0x084C, 0), /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__GPIO_6_27 */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8 */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__SJC_FAIL */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 1, 0x0850, 0), /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD2__GPIO_6_28 */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9 */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 1, 0x0854, 0), /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD3__GPIO_6_29 */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10 */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 1, 0x0844, 0), /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RXC__GPIO_6_30 */
    + IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A25__ECSPI4_SS1 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 2, 0x0000, 0), /* MX6Q_PAD_EIM_A25__ECSPI2_RDY */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A25__GPIO_5_2 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 6, 0x088C, 0), /* MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A25__PL301_PER1_HBURST_0 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 1, 0x0800, 0), /* MX6Q_PAD_EIM_EB2__ECSPI1_SS0 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 2, 0x07EC, 0), /* MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK */
    + IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 3, 0x08D4, 0), /* MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 4, 0x0890, 0), /* MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL */
    + IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB2__GPIO_2_30 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 6, 0x08A0, 0), /* MX6Q_PAD_EIM_EB2__I2C2_SCL */
    + IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 1, 0x07F4, 0), /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 3, 0x08D0, 0), /* MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 4, 0x0894, 0), /* MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D16__GPIO_3_16 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 6, 0x08A4, 0), /* MX6Q_PAD_EIM_D16__I2C2_SDA */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 1, 0x07F8, 0), /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 3, 0x08E0, 0), /* MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D17__GPIO_3_17 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 6, 0x08A8, 0), /* MX6Q_PAD_EIM_D17__I2C3_SCL */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D17__PL301_PER1_HBURST_1 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 1, 0x07FC, 0), /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 3, 0x08CC, 0), /* MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D18__GPIO_3_18 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 6, 0x08AC, 0), /* MX6Q_PAD_EIM_D18__I2C3_SDA */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D18__PL301_PER1_HBURST_2 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 1, 0x0804, 0), /* MX6Q_PAD_EIM_D19__ECSPI1_SS1 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 3, 0x08C8, 0), /* MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 4, 0x091C, 0), /* MX6Q_PAD_EIM_D19__UART1_CTS */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D19__EPIT1_EPITO */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D19__PL301_PER1_HRESP */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 1, 0x0824, 0), /* MX6Q_PAD_EIM_D20__ECSPI4_SS0 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 3, 0x08C4, 0), /* MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 4, 0x091C, 1), /* MX6Q_PAD_EIM_D20__UART1_RTS */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D20__GPIO_3_20 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D20__EPIT2_EPITO */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D21__ECSPI4_SCLK */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 3, 0x08B4, 0), /* MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 4, 0x0944, 0), /* MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D21__GPIO_3_21 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 6, 0x0898, 0), /* MX6Q_PAD_EIM_D21__I2C1_SCL */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 7, 0x0914, 0), /* MX6Q_PAD_EIM_D21__SPDIF_IN1 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D22__ECSPI4_MISO */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 3, 0x08B0, 0), /* MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D22__SPDIF_OUT1 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D22__PL301_PER1_HWRITE */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 2, 0x092C, 0), /* MX6Q_PAD_EIM_D23__UART3_CTS */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 3, 0x0000, 0), /* MX6Q_PAD_EIM_D23__UART1_DCD */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 4, 0x08D8, 0), /* MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D23__GPIO_3_23 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__ECSPI4_RDY */
    + IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 2, 0x092C, 1), /* MX6Q_PAD_EIM_EB3__UART3_RTS */
    + IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__UART1_RI */
    + IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 4, 0x08DC, 0), /* MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC */
    + IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__GPIO_2_31 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D24__ECSPI4_SS2 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D24__UART3_TXD */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 3, 0x0808, 0), /* MX6Q_PAD_EIM_D24__ECSPI1_SS2 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D24__ECSPI2_SS2 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D24__GPIO_3_24 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 6, 0x07D8, 0), /* MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D24__UART1_DTR */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D25__ECSPI4_SS3 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 2, 0x0930, 1), /* MX6Q_PAD_EIM_D25__UART3_RXD */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 3, 0x080C, 0), /* MX6Q_PAD_EIM_D25__ECSPI1_SS3 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D25__ECSPI2_SS3 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D25__GPIO_3_25 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 6, 0x07D4, 0), /* MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D25__UART1_DSR */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 3, 0x08C0, 0), /* MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D26__UART2_TXD */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D26__GPIO_3_26 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_SISG_2 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 3, 0x08BC, 0), /* MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 4, 0x0928, 1), /* MX6Q_PAD_EIM_D27__UART2_RXD */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D27__GPIO_3_27 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_SISG_3 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 1, 0x089C, 0), /* MX6Q_PAD_EIM_D28__I2C1_SDA */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D28__ECSPI4_MOSI */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 3, 0x08B8, 0), /* MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 4, 0x0924, 0), /* MX6Q_PAD_EIM_D28__UART2_CTS */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D28__GPIO_3_28 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 2, 0x0824, 1), /* MX6Q_PAD_EIM_D29__ECSPI4_SS0 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 4, 0x0924, 1), /* MX6Q_PAD_EIM_D29__UART2_RTS */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D29__GPIO_3_29 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 6, 0x08E4, 0), /* MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 3, 0x0000, 0), /* MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 4, 0x092C, 2), /* MX6Q_PAD_EIM_D30__UART3_CTS */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D30__GPIO_3_30 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 6, 0x0948, 0), /* MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D30__PL301_PER1_HPROT_0 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 4, 0x092C, 3), /* MX6Q_PAD_EIM_D31__UART3_RTS */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D31__GPIO_3_31 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR */
    + IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D31__PL301_PER1_HPROT_1 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 2, 0x08D4, 1), /* MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A24__IPU2_SISG_2 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A24__IPU1_SISG_2 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A24__GPIO_5_4 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A24__PL301_PER1_HPROT_2 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 2, 0x08D0, 1), /* MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A23__IPU2_SISG_3 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A23__IPU1_SISG_3 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A23__GPIO_6_6 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A23__PL301_PER1_HPROT_3 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 2, 0x08CC, 1), /* MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A22__GPIO_2_16 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 2, 0x08C8, 1), /* MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A21__RESERVED_RESERVED */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A21__GPIO_2_17 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 2, 0x08C4, 1), /* MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A20__RESERVED_RESERVED */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A20__GPIO_2_18 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 2, 0x08C0, 1), /* MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A19__RESERVED_RESERVED */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A19__GPIO_2_19 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 2, 0x08BC, 1), /* MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A18__RESERVED_RESERVED */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A18__GPIO_2_20 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 2, 0x08B8, 1), /* MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A17__RESERVED_RESERVED */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A17__GPIO_2_21 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 2, 0x08E0, 1), /* MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A16__GPIO_2_22 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 2, 0x0810, 0), /* MX6Q_PAD_EIM_CS0__ECSPI2_SCLK */
    + IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__GPIO_2_23 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 2, 0x0818, 0), /* MX6Q_PAD_EIM_CS1__ECSPI2_MOSI */
    + IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 4, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__GPIO_2_24 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 0, 0x0000, 0), /* MX6Q_PAD_EIM_OE__WEIM_WEIM_OE */
    + IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 1, 0x0000, 0), /* MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 2, 0x0814, 0), /* MX6Q_PAD_EIM_OE__ECSPI2_MISO */
    + IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 4, 0x0000, 0), /* MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 5, 0x0000, 0), /* MX6Q_PAD_EIM_OE__GPIO_2_25 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 6, 0x0000, 0), /* MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 0, 0x0000, 0), /* MX6Q_PAD_EIM_RW__WEIM_WEIM_RW */
    + IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 1, 0x0000, 0), /* MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 2, 0x081C, 0), /* MX6Q_PAD_EIM_RW__ECSPI2_SS0 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 4, 0x0000, 0), /* MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 5, 0x0000, 0), /* MX6Q_PAD_EIM_RW__GPIO_2_26 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 6, 0x0000, 0), /* MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 7, 0x0000, 0), /* MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 0, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA */
    + IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 1, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 2, 0x0820, 0), /* MX6Q_PAD_EIM_LBA__ECSPI2_SS1 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 5, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__GPIO_2_27 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 6, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 7, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 2, 0x08B4, 1), /* MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 4, 0x07F0, 0), /* MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY */
    + IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__GPIO_2_28 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 1, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 2, 0x08B0, 1), /* MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 3, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__GPIO_2_29 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 6, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__GPIO_3_0 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__USBPHY1_TX_LS_MODE */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__GPIO_3_1 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__USBPHY1_TX_HS_MODE */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__GPIO_3_2 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__USBPHY1_TX_HIZ */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__GPIO_3_3 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__GPIO_3_4 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__GPIO_3_5 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__GPIO_3_6 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__GPIO_3_7 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__GPIO_3_8 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__GPIO_3_9 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 2, 0x08D8, 1), /* MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__GPIO_3_10 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 2, 0x08DC, 1), /* MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__GPIO_3_11 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 2, 0x08E4, 1), /* MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__GPIO_3_12 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 2, 0x07EC, 1), /* MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__GPIO_3_13 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__GPIO_3_14 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__GPIO_3_15 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 0, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT */
    + IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 1, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B */
    + IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 5, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__GPIO_5_0 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 6, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 7, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 0, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK */
    + IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 1, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 5, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__GPIO_6_31 */
    + IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 6, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 */
    + IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 0, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DSP_CLK */
    + IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 1, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DSP_CLK */
    + IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 3, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 */
    + IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 4, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 */
    + IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 5, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 */
    + IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 6, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__MMDC_DEBUG_0 */
    + IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 */
    + IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 */
    + IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC */
    + IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 3, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 */
    + IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 */
    + IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__GPIO_4_17 */
    + IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 */
    + IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 */
    + IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 */
    + IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD */
    + IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 3, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 */
    + IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2 */
    + IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__GPIO_4_18 */
    + IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__MMDC_DEBUG_2 */
    + IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 7, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__PL301_PER1_HADDR_9 */
    + IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 */
    + IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 */
    + IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS */
    + IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 3, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 */
    + IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3 */
    + IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__GPIO_4_19 */
    + IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 */
    + IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 7, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__PL301_PER1_HADDR_10 */
    + IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 */
    + IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 */
    + IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD */
    + IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 3, 0x094C, 0), /* MX6Q_PAD_DI0_PIN4__USDHC1_WP */
    + IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD */
    + IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__GPIO_4_20 */
    + IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 */
    + IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 7, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__PL301_PER1_HADDR_11 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__GPIO_4_21 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__SDMA_DBG_EVT_CHNSL */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__GPIO_4_22 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__MMDC_DEBUG_6 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__PL301_PER1_HADR_12 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__GPIO_4_23 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__MMDC_DEBUG_7 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__PL301_PER1_HADR_13 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__SDMA_DBG_BUS_ERROR */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__GPIO_4_24 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__PL301_PER1_HADR_14 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__GPIO_4_25 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__PL301_PER1_HADR_15 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__SDMA_DBG_MCH_DMBUS */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__GPIO_4_26 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__MMDC_DEBUG_10 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__PL301_PER1_HADR_16 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__SDMA_DBG_RTBUF_WRT */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__GPIO_4_27 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__MMDC_DEBUG_11 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__PL301_PER1_HADR_17 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__SDMA_DBG_EVT_CHN_0 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__GPIO_4_28 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__MMDC_DEBUG_12 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__PL301_PER1_HADR_18 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__PWM1_PWMO */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__SDMA_DBG_EVT_CHN_1 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__GPIO_4_29 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__MMDC_DEBUG_13 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__PL301_PER1_HADR_19 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__PWM2_PWMO */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__SDMA_DBG_EVT_CHN_2 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__GPIO_4_30 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__MMDC_DEBUG_14 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__PL301_PER1_HADR_20 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__USDHC1_DBG_6 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__GPIO_4_31 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__MMDC_DEBUG_15 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__PL301_PER1_HADR21 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__GPIO_5_5 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__MMDC_DEBUG_16 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__PL301_PER1_HADR22 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__GPIO_5_6 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__MMDC_DEBUG_17 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__PL301_PER1_HADR23 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 3, 0x07D8, 1), /* MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__GPIO_5_7 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__MMDC_DEBUG_18 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__PL301_PER1_HADR24 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 3, 0x07D4, 1), /* MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__GPIO_5_8 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__MMDC_DEBUG_19 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 2, 0x0804, 1), /* MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 3, 0x0820, 1), /* MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__SDMA_DBG_EVT_CHN2 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__GPIO_5_9 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__MMDC_DEBUG_20 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__PL301_PER1_HADR25 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 2, 0x0818, 1), /* MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 3, 0x07DC, 0), /* MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 4, 0x090C, 0), /* MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__GPIO_5_10 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__MMDC_DEBUG_21 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__PL301_PER1_HADR26 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 2, 0x0814, 1), /* MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 3, 0x07D0, 0), /* MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 4, 0x0910, 0), /* MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__GPIO_5_11 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__MMDC_DEBUG_22 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__PL301_PER1_HADR27 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 2, 0x081C, 1), /* MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 3, 0x07E0, 0), /* MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 4, 0x07C0, 0), /* MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__GPIO_5_12 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__MMDC_DEBUG_23 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 2, 0x0810, 1), /* MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 3, 0x07CC, 0), /* MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 4, 0x07BC, 0), /* MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__GPIO_5_13 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__MMDC_DEBUG_24 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 2, 0x07F4, 1), /* MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 3, 0x07C4, 0), /* MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__SDMA_DBG_EVT_CHN7 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__GPIO_5_14 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__MMDC_DEBUG_25 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__PL301_PER1_HADR28 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 2, 0x07FC, 1), /* MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 3, 0x07B8, 1), /* MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__SDMA_DBG_BUS_DEV0 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__GPIO_5_15 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__MMDC_DEBUG_26 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__PL301_PER1_HADR29 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 2, 0x07F8, 1), /* MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 3, 0x07C8, 1), /* MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__SDMA_DBG_BUS_DEV1 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__GPIO_5_16 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__MMDC_DEBUG_27 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__PL301_PER1_HADR30 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 2, 0x0800, 1), /* MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 3, 0x07B4, 1), /* MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__SDMA_DBG_BUS_DEV2 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__GPIO_5_17 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__MMDC_DEBUG_28 */
    + IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__PL301_PER1_HADR31 */
    + IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 0, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED */
    + IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 1, 0x0840, 0), /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */
    + IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 2, 0x086C, 0), /* MX6Q_PAD_ENET_MDIO__ESAI1_SCKR */
    + IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 3, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEV3 */
    + IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 4, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__ENET_1588_EVT1_OUT */
    + IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 5, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__GPIO_1_22 */
    + IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 6, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK */
    + IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 0, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__RESERVED_RSRVED */
    + IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 1, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
    + IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 2, 0x085C, 0), /* MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR */
    + IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 3, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__SDMA_DBGBUS_DEV4 */
    + IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 5, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 */
    + IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 6, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK */
    + IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 7, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__USBPHY1_RX_SQH */
    + IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 1, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__ENET_RX_ER */
    + IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 2, 0x0864, 0), /* MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR */
    + IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 3, 0x0914, 1), /* MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 */
    + IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 4, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__ENET_1588_EVT2_OUT */
    + IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 5, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__GPIO_1_24 */
    + IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 6, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__PHY_TDI */
    + IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 7, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__USBPHY1_RX_HS_RXD */
    + IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 0, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__RESERVED_RSRVED */
    + IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 1, 0x0858, 1), /* MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN */
    + IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 2, 0x0870, 0), /* MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT */
    + IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 3, 0x0918, 1), /* MX6Q_PAD_ENET_CRS_DV__SPDIF_EXTCLK */
    + IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 5, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 */
    + IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 6, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__PHY_TDO */
    + IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 7, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__USBPHY1_RX_FS_RXD */
    + IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 0, 0x0908, 0), /* MX6Q_PAD_ENET_RXD1__MLB_MLBSIG */
    + IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 1, 0x084C, 1), /* MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 */
    + IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 2, 0x0860, 0), /* MX6Q_PAD_ENET_RXD1__ESAI1_FST */
    + IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 4, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__ENET_1588_EVT3_OUT */
    + IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 5, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__GPIO_1_26 */
    + IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 6, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__PHY_TCK */
    + IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 7, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__USBPHY1_RX_DISCON */
    + IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 0, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT */
    + IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 1, 0x0848, 1), /* MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 */
    + IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 2, 0x0868, 0), /* MX6Q_PAD_ENET_RXD0__ESAI1_HCKT */
    + IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 3, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 */
    + IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 5, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__GPIO_1_27 */
    + IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 6, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__PHY_TMS */
    + IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 7, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__USBPHY1_PLL_CK20DIV */
    + IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 0, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__RESERVED_RSRVED */
    + IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 1, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__ENET_TX_EN */
    + IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 2, 0x0880, 0), /* MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 */
    + IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 5, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__GPIO_1_28 */
    + IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 6, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI */
    + IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 7, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__USBPHY2_RX_SQH */
    + IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 0, 0x0900, 0), /* MX6Q_PAD_ENET_TXD1__MLB_MLBCLK */
    + IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 1, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 */
    + IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 2, 0x087C, 0), /* MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 */
    + IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 4, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN */
    + IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 5, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__GPIO_1_29 */
    + IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 6, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO */
    + IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 7, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__USBPHY2_RX_HS_RXD */
    + IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 0, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__RESERVED_RSRVED */
    + IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 1, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 */
    + IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 2, 0x0884, 0), /* MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 */
    + IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 5, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__GPIO_1_30 */
    + IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 6, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK */
    + IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 7, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__USBPHY2_RX_FS_RXD */
    + IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 0, 0x0904, 0), /* MX6Q_PAD_ENET_MDC__MLB_MLBDAT */
    + IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 1, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__ENET_MDC */
    + IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 2, 0x0888, 0), /* MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 */
    + IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 4, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN */
    + IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 5, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__GPIO_1_31 */
    + IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 6, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__SATA_PHY_TMS */
    + IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 7, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__USBPHY2_RX_DISCON */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D40, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D41, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D42, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D43, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D44, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D45, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D46, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D47, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS5, 0x050C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_DQM5, 0x0510, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D32, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D33, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D34, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D35, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D36, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D37, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D38, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D39, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_DQM4, 0x0514, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS4, 0x0518, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D24, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D25, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D26, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D27, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D28, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D29, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS3, 0x051C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D30, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D31, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_DQM3, 0x0520, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D16, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D17, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D18, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D19, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D20, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D21, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D22, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS2, 0x0524, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D23, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_DQM2, 0x0528, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_A0, 0x052C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_A1, 0x0530, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_A2, 0x0534, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_A3, 0x0538, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_A4, 0x053C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_A5, 0x0540, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_A6, 0x0544, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_A7, 0x0548, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_A8, 0x054C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_A9, 0x0550, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_A10, 0x0554, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_A11, 0x0558, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_A12, 0x055C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_A13, 0x0560, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_A14, 0x0564, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_A15, 0x0568, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_CAS, 0x056C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_CS0, 0x0570, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_CS1, 0x0574, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_RAS, 0x0578, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_RESET, 0x057C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_SDBA0, 0x0580, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_SDBA1, 0x0584, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_SDCLK_0, 0x0588, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_SDBA2, 0x058C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_SDCKE0, 0x0590, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_SDCLK_1, 0x0594, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_SDCKE1, 0x0598, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_SDODT0, 0x059C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_SDODT1, 0x05A0, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_SDWE, 0x05A4, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D0, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D1, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D2, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D3, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D4, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D5, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS0, 0x05A8, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D6, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D7, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_DQM0, 0x05AC, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D8, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D9, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D10, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D11, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D12, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D13, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D14, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS1, 0x05B0, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D15, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_DQM1, 0x05B4, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D48, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D49, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D50, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D51, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D52, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D53, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D54, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D55, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS6, 0x05B8, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_DQM6, 0x05BC, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D56, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS7, 0x05C0, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D57, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D58, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D59, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D60, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_DQM7, 0x05C4, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D61, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D62, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 */
    + IMX_PIN_REG(MX6Q_PAD_DRAM_D63, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 0, 0x07F4, 2), /* MX6Q_PAD_KEY_COL0__ECSPI1_SCLK */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 1, 0x0854, 1), /* MX6Q_PAD_KEY_COL0__ENET_RDATA_3 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 2, 0x07DC, 1), /* MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__KPP_COL_0 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 4, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__UART4_TXD */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__GPIO_4_6 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 0, 0x07FC, 2), /* MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 2, 0x07D0, 1), /* MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__KPP_ROW_0 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 4, 0x0938, 1), /* MX6Q_PAD_KEY_ROW0__UART4_RXD */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__GPIO_4_7 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__PL301_PER1_HADR_0 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 0, 0x07F8, 2), /* MX6Q_PAD_KEY_COL1__ECSPI1_MISO */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 1, 0x0840, 1), /* MX6Q_PAD_KEY_COL1__ENET_MDIO */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 2, 0x07E0, 1), /* MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__KPP_COL_1 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 4, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__UART5_TXD */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__GPIO_4_8 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__USDHC1_VSELECT */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__PL301MX_PER1_HADR_1 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 0, 0x0800, 2), /* MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__ENET_COL */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 2, 0x07CC, 1), /* MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__KPP_ROW_1 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 4, 0x0940, 1), /* MX6Q_PAD_KEY_ROW1__UART5_RXD */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__GPIO_4_9 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__PL301_PER1_HADDR_2 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 0, 0x0804, 2), /* MX6Q_PAD_KEY_COL2__ECSPI1_SS1 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 1, 0x0850, 1), /* MX6Q_PAD_KEY_COL2__ENET_RDATA_2 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 2, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__CAN1_TXCAN */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__KPP_COL_2 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 4, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__ENET_MDC */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__GPIO_4_10 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__USBOH3_H1_PWRCTL_WKP */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__PL301_PER1_HADDR_3 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 0, 0x0808, 1), /* MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 2, 0x07E4, 0), /* MX6Q_PAD_KEY_ROW2__CAN1_RXCAN */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__KPP_ROW_2 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 4, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__GPIO_4_11 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 6, 0x088C, 1), /* MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__PL301_PER1_HADR_4 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 0, 0x080C, 1), /* MX6Q_PAD_KEY_COL3__ECSPI1_SS3 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 1, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__ENET_CRS */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 2, 0x0890, 1), /* MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__KPP_COL_3 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 4, 0x08A0, 1), /* MX6Q_PAD_KEY_COL3__I2C2_SCL */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__GPIO_4_12 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 6, 0x0914, 2), /* MX6Q_PAD_KEY_COL3__SPDIF_IN1 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__PL301_PER1_HADR_5 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 0, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 1, 0x07B0, 0), /* MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 2, 0x0894, 1), /* MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__KPP_ROW_3 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 4, 0x08A4, 1), /* MX6Q_PAD_KEY_ROW3__I2C2_SDA */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__GPIO_4_13 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__PL301_PER1_HADR_6 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 0, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__CAN2_TXCAN */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 1, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__IPU1_SISG_4 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 2, 0x0944, 1), /* MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__KPP_COL_4 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 4, 0x093C, 0), /* MX6Q_PAD_KEY_COL4__UART5_RTS */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__GPIO_4_14 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__MMDC_DEBUG_49 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__PL301_PER1_HADDR_7 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 0, 0x07E8, 0), /* MX6Q_PAD_KEY_ROW4__CAN2_RXCAN */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 2, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__KPP_ROW_4 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 4, 0x093C, 1), /* MX6Q_PAD_KEY_ROW4__UART5_CTS */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__GPIO_4_15 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__MMDC_DEBUG_50 */
    + IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__PL301_PER1_HADR_8 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 0, 0x0000, 0), /* MX6Q_PAD_GPIO_0__CCM_CLKO */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 2, 0x08E8, 0), /* MX6Q_PAD_GPIO_0__KPP_COL_5 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 3, 0x07B0, 1), /* MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_0__EPIT1_EPITO */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_0__GPIO_1_0 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 0, 0x086C, 1), /* MX6Q_PAD_GPIO_1__ESAI1_SCKR */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_1__WDOG2_WDOG_B */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 2, 0x08F4, 0), /* MX6Q_PAD_GPIO_1__KPP_ROW_5 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_1__PWM2_PWMO */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_1__GPIO_1_1 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_1__USDHC1_CD */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_1__SRC_TESTER_ACK */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 0, 0x085C, 1), /* MX6Q_PAD_GPIO_9__ESAI1_FSR */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_9__WDOG1_WDOG_B */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 2, 0x08EC, 0), /* MX6Q_PAD_GPIO_9__KPP_COL_6 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_9__CCM_REF_EN_B */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_9__PWM1_PWMO */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_9__GPIO_1_9 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 6, 0x094C, 1), /* MX6Q_PAD_GPIO_9__USDHC1_WP */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_9__SRC_EARLY_RST */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 0, 0x0864, 1), /* MX6Q_PAD_GPIO_3__ESAI1_HCKR */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 2, 0x08A8, 1), /* MX6Q_PAD_GPIO_3__I2C3_SCL */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_3__ANATOP_24M_OUT */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_3__CCM_CLKO2 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_3__GPIO_1_3 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 6, 0x0948, 1), /* MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 7, 0x0900, 1), /* MX6Q_PAD_GPIO_3__MLB_MLBCLK */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 0, 0x0870, 1), /* MX6Q_PAD_GPIO_6__ESAI1_SCKT */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 2, 0x08AC, 1), /* MX6Q_PAD_GPIO_6__I2C3_SDA */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_6__GPIO_1_6 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_6__USDHC2_LCTL */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 7, 0x0908, 1), /* MX6Q_PAD_GPIO_6__MLB_MLBSIG */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 0, 0x0860, 1), /* MX6Q_PAD_GPIO_2__ESAI1_FST */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 2, 0x08F8, 1), /* MX6Q_PAD_GPIO_2__KPP_ROW_6 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_2__GPIO_1_2 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_2__USDHC2_WP */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 7, 0x0904, 1), /* MX6Q_PAD_GPIO_2__MLB_MLBDAT */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 0, 0x0868, 1), /* MX6Q_PAD_GPIO_4__ESAI1_HCKT */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 2, 0x08F0, 1), /* MX6Q_PAD_GPIO_4__KPP_COL_7 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_4__GPIO_1_4 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_4__USDHC2_CD */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 0, 0x087C, 1), /* MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 2, 0x08FC, 1), /* MX6Q_PAD_GPIO_5__KPP_ROW_7 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_5__CCM_CLKO */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_5__GPIO_1_5 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 6, 0x08A8, 2), /* MX6Q_PAD_GPIO_5__I2C3_SCL */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_5__CHEETAH_EVENTI */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 0, 0x0884, 1), /* MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_7__ECSPI5_RDY */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_7__EPIT1_EPITO */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_7__CAN1_TXCAN */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_7__UART2_TXD */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_7__GPIO_1_7 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_7__SPDIF_PLOCK */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 0, 0x0888, 1), /* MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_8__EPIT2_EPITO */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 3, 0x07E4, 1), /* MX6Q_PAD_GPIO_8__CAN1_RXCAN */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 4, 0x0928, 3), /* MX6Q_PAD_GPIO_8__UART2_RXD */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_8__GPIO_1_8 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_8__SPDIF_SRCLK */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_8__USBOH3_OTG_PWRCTL_WAK */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 0, 0x0880, 1), /* MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 2, 0x083C, 1), /* MX6Q_PAD_GPIO_16__ENET_ETHERNET_REF_OUT */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_16__USDHC1_LCTL */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 4, 0x0914, 3), /* MX6Q_PAD_GPIO_16__SPDIF_IN1 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_16__GPIO_7_11 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 6, 0x08AC, 2), /* MX6Q_PAD_GPIO_16__I2C3_SDA */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_16__SJC_DE_B */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 0, 0x0874, 0), /* MX6Q_PAD_GPIO_17__ESAI1_TX0 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 2, 0x07F0, 1), /* MX6Q_PAD_GPIO_17__CCM_PMIC_RDY */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 3, 0x090C, 1), /* MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_17__SPDIF_OUT1 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_17__GPIO_7_12 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_17__SJC_JTAG_ACT */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 0, 0x0878, 0), /* MX6Q_PAD_GPIO_18__ESAI1_TX1 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 1, 0x0844, 1), /* MX6Q_PAD_GPIO_18__ENET_RX_CLK */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_18__USDHC3_VSELECT */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 3, 0x0910, 1), /* MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 4, 0x07B0, 2), /* MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_18__GPIO_7_13 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_18__SNVS_HP_WRA_SNVS_VIO5 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 0, 0x08E8, 1), /* MX6Q_PAD_GPIO_19__KPP_COL_5 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_19__SPDIF_OUT1 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_19__CCM_CLKO */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_19__ECSPI1_RDY */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_19__GPIO_4_5 */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_19__ENET_TX_ER */
    + IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_19__SRC_INT_BOOT */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK___MMDC_DEBUG_29 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__CCM_CLKO */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__GPIO_5_19 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__MMDC_DEBUG_31 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__MMDC_DEBUG_32 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 2, 0x07F4, 3), /* MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 3, 0x08E8, 2), /* MX6Q_PAD_CSI0_DAT4__KPP_COL_5 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__GPIO_5_22 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__MMDC_DEBUG_43 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 2, 0x07FC, 3), /* MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 3, 0x08F4, 1), /* MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__GPIO_5_23 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 2, 0x07F8, 3), /* MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 3, 0x08EC, 1), /* MX6Q_PAD_CSI0_DAT6__KPP_COL_6 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__GPIO_5_24 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 2, 0x0800, 3), /* MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 3, 0x08F8, 2), /* MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__GPIO_5_25 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 2, 0x0810, 2), /* MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 3, 0x08F0, 2), /* MX6Q_PAD_CSI0_DAT8__KPP_COL_7 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 4, 0x089C, 1), /* MX6Q_PAD_CSI0_DAT8__I2C1_SDA */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__GPIO_5_26 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 2, 0x0818, 2), /* MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 3, 0x08FC, 2), /* MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 4, 0x0898, 1), /* MX6Q_PAD_CSI0_DAT9__I2C1_SCL */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__GPIO_5_27 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 2, 0x0814, 2), /* MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__GPIO_5_28 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 2, 0x081C, 2), /* MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 3, 0x0920, 1), /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__GPIO_5_29 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__UART4_TXD */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__GPIO_5_30 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 3, 0x0938, 3), /* MX6Q_PAD_CSI0_DAT13__UART4_RXD */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__GPIO_5_31 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__UART5_TXD */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__GPIO_6_0 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 3, 0x0940, 3), /* MX6Q_PAD_CSI0_DAT15__UART5_RXD */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__GPIO_6_1 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 3, 0x0934, 0), /* MX6Q_PAD_CSI0_DAT16__UART4_RTS */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__GPIO_6_2 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 3, 0x0934, 1), /* MX6Q_PAD_CSI0_DAT17__UART4_CTS */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__GPIO_6_3 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 3, 0x093C, 2), /* MX6Q_PAD_CSI0_DAT18__UART5_RTS */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__GPIO_6_4 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 3, 0x093C, 3), /* MX6Q_PAD_CSI0_DAT19__UART5_CTS */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__GPIO_6_5 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 */
    + IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__ANATOP_TESTO_9 */
    + IMX_PIN_REG(MX6Q_PAD_JTAG_TMS, 0x0678, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TMS__SJC_TMS */
    + IMX_PIN_REG(MX6Q_PAD_JTAG_MOD, 0x067C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_MOD__SJC_MOD */
    + IMX_PIN_REG(MX6Q_PAD_JTAG_TRSTB, 0x0680, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB */
    + IMX_PIN_REG(MX6Q_PAD_JTAG_TDI, 0x0684, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TDI__SJC_TDI */
    + IMX_PIN_REG(MX6Q_PAD_JTAG_TCK, 0x0688, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TCK__SJC_TCK */
    + IMX_PIN_REG(MX6Q_PAD_JTAG_TDO, 0x068C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TDO__SJC_TDO */
    + IMX_PIN_REG(MX6Q_PAD_LVDS1_TX3_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 */
    + IMX_PIN_REG(MX6Q_PAD_LVDS1_TX2_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 */
    + IMX_PIN_REG(MX6Q_PAD_LVDS1_CLK_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK */
    + IMX_PIN_REG(MX6Q_PAD_LVDS1_TX1_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 */
    + IMX_PIN_REG(MX6Q_PAD_LVDS1_TX0_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 */
    + IMX_PIN_REG(MX6Q_PAD_LVDS0_TX3_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 */
    + IMX_PIN_REG(MX6Q_PAD_LVDS0_CLK_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK */
    + IMX_PIN_REG(MX6Q_PAD_LVDS0_TX2_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 */
    + IMX_PIN_REG(MX6Q_PAD_LVDS0_TX1_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 */
    + IMX_PIN_REG(MX6Q_PAD_LVDS0_TX0_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 */
    + IMX_PIN_REG(MX6Q_PAD_TAMPER, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_TAMPER__SNVS_LP_WRAP_SNVS_TD1 */
    + IMX_PIN_REG(MX6Q_PAD_PMIC_ON_REQ, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_PMIC_ON_REQ__SNVS_LPWRAP_WKALM */
    + IMX_PIN_REG(MX6Q_PAD_PMIC_STBY_REQ, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_STBYRQ */
    + IMX_PIN_REG(MX6Q_PAD_POR_B, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_POR_B__SRC_POR_B */
    + IMX_PIN_REG(MX6Q_PAD_BOOT_MODE1, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 */
    + IMX_PIN_REG(MX6Q_PAD_RESET_IN_B, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_RESET_IN_B__SRC_RESET_B */
    + IMX_PIN_REG(MX6Q_PAD_BOOT_MODE0, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 */
    + IMX_PIN_REG(MX6Q_PAD_TEST_MODE, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_TEST_MODE__TCU_TEST_MODE */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 1, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__UART1_TXD */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__PCIE_CTRL_MUX_24 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__GPIO_6_17 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USBPHY2_CLK20DIV */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 1, 0x0920, 3), /* MX6Q_PAD_SD3_DAT6__UART1_RXD */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__PCIE_CTRL_MUX_25 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__GPIO_6_18 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__ANATOP_TESTO_10 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 1, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__UART2_TXD */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__PCIE_CTRL_MUX_26 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__ANATOP_TESTO_11 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 1, 0x0928, 5), /* MX6Q_PAD_SD3_DAT4__UART2_RXD */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__PCIE_CTRL_MUX_27 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__ANATOP_TESTO_12 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 0, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
    + IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 1, 0x0924, 2), /* MX6Q_PAD_SD3_CMD__UART2_CTS */
    + IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 2, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__CAN1_TXCAN */
    + IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 3, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 4, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 5, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__GPIO_7_2 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 6, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 7, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__ANATOP_TESTO_13 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 0, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
    + IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 1, 0x0924, 3), /* MX6Q_PAD_SD3_CLK__UART2_RTS */
    + IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 2, 0x07E4, 2), /* MX6Q_PAD_SD3_CLK__CAN1_RXCAN */
    + IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 3, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 4, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 5, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__GPIO_7_3 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 6, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 7, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__ANATOP_TESTO_14 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 1, 0x091C, 2), /* MX6Q_PAD_SD3_DAT0__UART1_CTS */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__CAN2_TXCAN */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__GPIO_7_4 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__ANATOP_TESTO_15 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 1, 0x091C, 3), /* MX6Q_PAD_SD3_DAT1__UART1_RTS */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 2, 0x07E8, 1), /* MX6Q_PAD_SD3_DAT1__CAN2_RXCAN */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__GPIO_7_5 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__ANATOP_TESTI_0 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__PCIE_CTRL_MUX_28 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__GPIO_7_6 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__ANATOP_TESTI_1 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 1, 0x092C, 4), /* MX6Q_PAD_SD3_DAT3__UART3_CTS */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__PCIE_CTRL_MUX_29 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__GPIO_7_7 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__ANATOP_TESTI_2 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 0, 0x0000, 0), /* MX6Q_PAD_SD3_RST__USDHC3_RST */
    + IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 1, 0x092C, 5), /* MX6Q_PAD_SD3_RST__UART3_RTS */
    + IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 2, 0x0000, 0), /* MX6Q_PAD_SD3_RST__PCIE_CTRL_MUX_30 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 3, 0x0000, 0), /* MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 4, 0x0000, 0), /* MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 5, 0x0000, 0), /* MX6Q_PAD_SD3_RST__GPIO_7_8 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 6, 0x0000, 0), /* MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22 */
    + IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 7, 0x0000, 0), /* MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__PCIE_CTRL_MUX_31 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__GPIO_6_7 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__USDHC4_RST */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__PCIE_CTRL_MUX_0 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__GPIO_6_8 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__GPIO_6_9 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__PCIE_CTRL_MUX_2 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__GPIO_6_10 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__PL301_PER1_HSIZE_1 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OT15 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OT15 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__PL301_PER1_HSIZE_2 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__PCIE_CTRL_MUX_3 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__PL301_PER1_HRDYOUT */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 2, 0x0874, 1), /* MX6Q_PAD_NANDF_CS2__ESAI1_TX0 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__CCM_CLKO2 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__GPIO_6_15 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 2, 0x0878, 1), /* MX6Q_PAD_NANDF_CS3__ESAI1_TX1 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__PCIE_CTRL_MUX_4 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__GPIO_6_16 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__TPSMP_CLK */
    + IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 0, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
    + IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 1, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
    + IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 2, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__UART3_TXD */
    + IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 4, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__PCIE_CTRL_MUX_5 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 5, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__GPIO_7_9 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 7, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR */
    + IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 0, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
    + IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 1, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
    + IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 2, 0x0930, 3), /* MX6Q_PAD_SD4_CLK__UART3_RXD */
    + IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 4, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__PCIE_CTRL_MUX_6 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 5, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__GPIO_7_10 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__USDHC1_DAT4 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT16 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT16 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__USDHC1_DAT5 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT17 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT17 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__USDHC1_DAT6 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT18 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT18 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__USDHC1_DAT7 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT19 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT19 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT20 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT20 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__GPIO_2_4 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT21 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT21 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__GPIO_2_5 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT22 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT22 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT23 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT23 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 */
    + IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__RAWNAND_D8 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT24 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT24 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__GPIO_2_8 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__RAWNAND_D9 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__PWM3_PWMO */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT25 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT25 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__GPIO_2_9 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__RAWNAND_D10 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__PWM4_PWMO */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT26 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT26 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__GPIO_2_10 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__RAWNAND_D11 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT27 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT27 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__GPIO_2_11 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__RAWNAND_D12 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 2, 0x0928, 6), /* MX6Q_PAD_SD4_DAT4__UART2_RXD */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__GPIO_2_12 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__RAWNAND_D13 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 2, 0x0924, 4), /* MX6Q_PAD_SD4_DAT5__UART2_RTS */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__GPIO_2_13 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__RAWNAND_D14 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 2, 0x0924, 5), /* MX6Q_PAD_SD4_DAT6__UART2_CTS */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__GPIO_2_14 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__RAWNAND_D15 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__UART2_TXD */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__GPIO_2_15 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 */
    + IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 */
    + IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 */
    + IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 1, 0x0834, 1), /* MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 */
    + IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__PWM3_PWMO */
    + IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 */
    + IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__PCIE_CTRL_MUX_7 */
    + IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__GPIO_1_17 */
    + IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 */
    + IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__ANATOP_TESTO_8 */
    + IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 */
    + IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 1, 0x082C, 1), /* MX6Q_PAD_SD1_DAT0__ECSPI5_MISO */
    + IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS */
    + IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 */
    + IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__PCIE_CTRL_MUX_8 */
    + IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__GPIO_1_16 */
    + IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 */
    + IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__ANATOP_TESTO_7 */
    + IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 */
    + IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 1, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 */
    + IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 */
    + IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__PWM1_PWMO */
    + IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B */
    + IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__GPIO_1_21 */
    + IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB */
    + IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__ANATOP_TESTO_6 */
    + IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 0, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__USDHC1_CMD */
    + IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 1, 0x0830, 0), /* MX6Q_PAD_SD1_CMD__ECSPI5_MOSI */
    + IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 2, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__PWM4_PWMO */
    + IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 3, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 */
    + IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 5, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__GPIO_1_18 */
    + IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 7, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__ANATOP_TESTO_5 */
    + IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 */
    + IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 1, 0x0838, 1), /* MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 */
    + IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 */
    + IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__PWM2_PWMO */
    + IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B */
    + IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__GPIO_1_19 */
    + IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB */
    + IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__ANATOP_TESTO_4 */
    + IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 0, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__USDHC1_CLK */
    + IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 1, 0x0828, 0), /* MX6Q_PAD_SD1_CLK__ECSPI5_SCLK */
    + IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 2, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT */
    + IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 3, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__GPT_CLKIN */
    + IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 5, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__GPIO_1_20 */
    + IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 6, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__PHY_DTB_0 */
    + IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 7, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 */
    + IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 0, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
    + IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 1, 0x0828, 1), /* MX6Q_PAD_SD2_CLK__ECSPI5_SCLK */
    + IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 2, 0x08E8, 3), /* MX6Q_PAD_SD2_CLK__KPP_COL_5 */
    + IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 3, 0x07C0, 1), /* MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS */
    + IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 4, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__PCIE_CTRL_MUX_9 */
    + IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 5, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__GPIO_1_10 */
    + IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 6, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__PHY_DTB_1 */
    + IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 7, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 */
    + IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 0, 0x0000, 0), /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
    + IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 1, 0x0830, 1), /* MX6Q_PAD_SD2_CMD__ECSPI5_MOSI */
    + IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 2, 0x08F4, 2), /* MX6Q_PAD_SD2_CMD__KPP_ROW_5 */
    + IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 3, 0x07BC, 1), /* MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC */
    + IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 4, 0x0000, 0), /* MX6Q_PAD_SD2_CMD__PCIE_CTRL_MUX_10 */
    + IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 5, 0x0000, 0), /* MX6Q_PAD_SD2_CMD__GPIO_1_11 */
    + IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
    + IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 1, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 */
    + IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 2, 0x08EC, 2), /* MX6Q_PAD_SD2_DAT3__KPP_COL_6 */
    + IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 3, 0x07C4, 1), /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
    + IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 4, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__PCIE_CTRL_MUX_11 */
    + IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__GPIO_1_12 */
    + IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__SJC_DONE */
    + IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__ANATOP_TESTO_3 */
    +};
    +
    +/* Pad names for the pinmux subsystem */
    +static const struct pinctrl_pin_desc imx6q_pinctrl_pads[] = {
    + IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT1),
    + IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT2),
    + IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT0),
    + IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TXC),
    + IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD0),
    + IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD1),
    + IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD2),
    + IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD3),
    + IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RX_CTL),
    + IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD0),
    + IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TX_CTL),
    + IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD1),
    + IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD2),
    + IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD3),
    + IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RXC),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A25),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB2),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D16),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D17),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D18),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D19),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D20),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D21),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D22),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D23),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB3),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D24),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D25),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D26),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D27),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D28),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D29),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D30),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D31),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A24),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A23),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A22),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A21),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A20),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A19),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A18),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A17),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A16),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_CS0),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_CS1),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_OE),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_RW),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_LBA),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB0),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB1),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA0),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA1),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA2),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA3),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA4),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA5),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA6),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA7),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA8),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA9),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA10),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA11),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA12),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA13),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA14),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA15),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_WAIT),
    + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_BCLK),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DI0_DISP_CLK),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN15),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN2),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN3),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN4),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT0),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT1),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT2),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT3),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT4),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT5),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT6),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT7),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT8),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT9),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT10),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT11),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT12),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT13),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT14),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT15),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT16),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT17),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT18),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT19),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT20),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT21),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT22),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT23),
    + IMX_PINCTRL_PIN(MX6Q_PAD_ENET_MDIO),
    + IMX_PINCTRL_PIN(MX6Q_PAD_ENET_REF_CLK),
    + IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RX_ER),
    + IMX_PINCTRL_PIN(MX6Q_PAD_ENET_CRS_DV),
    + IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RXD1),
    + IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RXD0),
    + IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TX_EN),
    + IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD1),
    + IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD0),
    + IMX_PINCTRL_PIN(MX6Q_PAD_ENET_MDC),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D40),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D41),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D42),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D43),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D44),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D45),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D46),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D47),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS5),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM5),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D32),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D33),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D34),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D35),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D36),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D37),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D38),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D39),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM4),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS4),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D24),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D25),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D26),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D27),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D28),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D29),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS3),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D30),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D31),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM3),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D16),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D17),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D18),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D19),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D20),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D21),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D22),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS2),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D23),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM2),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A0),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A1),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A2),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A3),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A4),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A5),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A6),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A7),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A8),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A9),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A10),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A11),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A12),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A13),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A14),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A15),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_CAS),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_CS0),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_CS1),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_RAS),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_RESET),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDBA0),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDBA1),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCLK_0),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDBA2),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCKE0),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCLK_1),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCKE1),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDODT0),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDODT1),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDWE),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D0),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D1),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D2),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D3),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D4),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D5),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS0),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D6),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D7),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM0),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D8),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D9),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D10),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D11),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D12),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D13),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D14),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS1),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D15),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM1),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D48),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D49),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D50),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D51),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D52),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D53),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D54),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D55),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS6),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM6),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D56),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS7),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D57),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D58),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D59),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D60),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM7),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D61),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D62),
    + IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D63),
    + IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL0),
    + IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW0),
    + IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL1),
    + IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW1),
    + IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL2),
    + IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW2),
    + IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL3),
    + IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW3),
    + IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL4),
    + IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW4),
    + IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_0),
    + IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_1),
    + IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_9),
    + IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_3),
    + IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_6),
    + IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_2),
    + IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_4),
    + IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_5),
    + IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_7),
    + IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_8),
    + IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_16),
    + IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_17),
    + IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_18),
    + IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_19),
    + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_PIXCLK),
    + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_MCLK),
    + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DATA_EN),
    + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_VSYNC),
    + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT4),
    + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT5),
    + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT6),
    + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT7),
    + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT8),
    + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT9),
    + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT10),
    + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT11),
    + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT12),
    + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT13),
    + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT14),
    + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT15),
    + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT16),
    + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT17),
    + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT18),
    + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT19),
    + IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TMS),
    + IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_MOD),
    + IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TRSTB),
    + IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TDI),
    + IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TCK),
    + IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TDO),
    + IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX3_P),
    + IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX2_P),
    + IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_CLK_P),
    + IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX1_P),
    + IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX0_P),
    + IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX3_P),
    + IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_CLK_P),
    + IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX2_P),
    + IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX1_P),
    + IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX0_P),
    + IMX_PINCTRL_PIN(MX6Q_PAD_TAMPER),
    + IMX_PINCTRL_PIN(MX6Q_PAD_PMIC_ON_REQ),
    + IMX_PINCTRL_PIN(MX6Q_PAD_PMIC_STBY_REQ),
    + IMX_PINCTRL_PIN(MX6Q_PAD_POR_B),
    + IMX_PINCTRL_PIN(MX6Q_PAD_BOOT_MODE1),
    + IMX_PINCTRL_PIN(MX6Q_PAD_RESET_IN_B),
    + IMX_PINCTRL_PIN(MX6Q_PAD_BOOT_MODE0),
    + IMX_PINCTRL_PIN(MX6Q_PAD_TEST_MODE),
    + IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT7),
    + IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT6),
    + IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT5),
    + IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT4),
    + IMX_PINCTRL_PIN(MX6Q_PAD_SD3_CMD),
    + IMX_PINCTRL_PIN(MX6Q_PAD_SD3_CLK),
    + IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT0),
    + IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT1),
    + IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT2),
    + IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT3),
    + IMX_PINCTRL_PIN(MX6Q_PAD_SD3_RST),
    + IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CLE),
    + IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_ALE),
    + IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_WP_B),
    + IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_RB0),
    + IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS0),
    + IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS1),
    + IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS2),
    + IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS3),
    + IMX_PINCTRL_PIN(MX6Q_PAD_SD4_CMD),
    + IMX_PINCTRL_PIN(MX6Q_PAD_SD4_CLK),
    + IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D0),
    + IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D1),
    + IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D2),
    + IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D3),
    + IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D4),
    + IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D5),
    + IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D6),
    + IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D7),
    + IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT0),
    + IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT1),
    + IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT2),
    + IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT3),
    + IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT4),
    + IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT5),
    + IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT6),
    + IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT7),
    + IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT1),
    + IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT0),
    + IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT3),
    + IMX_PINCTRL_PIN(MX6Q_PAD_SD1_CMD),
    + IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT2),
    + IMX_PINCTRL_PIN(MX6Q_PAD_SD1_CLK),
    + IMX_PINCTRL_PIN(MX6Q_PAD_SD2_CLK),
    + IMX_PINCTRL_PIN(MX6Q_PAD_SD2_CMD),
    + IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT3),
    +};
    +
    +static struct imx_pinctrl_soc_info imx6q_pinctrl_info = {
    + .pins = imx6q_pinctrl_pads,
    + .npins = ARRAY_SIZE(imx6q_pinctrl_pads),
    + .pin_regs = imx6q_pin_regs,
    + .npin_regs = ARRAY_SIZE(imx6q_pin_regs),
    +};
    +
    +static struct of_device_id imx6q_pinctrl_of_match[] __devinitdata = {
    + { .compatible = "fsl,imx6q-iomuxc", },
    + { /* sentinel */ }
    +};
    +
    +static int __devinit imx6q_pinctrl_probe(struct platform_device *pdev)
    +{
    + return imx_pinctrl_probe(pdev, &imx6q_pinctrl_info);
    +}
    +
    +static struct platform_driver imx6q_pinctrl_driver = {
    + .driver = {
    + .name = "imx6q-pinctrl",
    + .owner = THIS_MODULE,
    + .of_match_table = of_match_ptr(imx6q_pinctrl_of_match),
    + },
    + .probe = imx6q_pinctrl_probe,
    + .remove = __devexit_p(imx_pinctrl_remove),
    +};
    +
    +static int __init imx6q_pinctrl_init(void)
    +{
    + return platform_driver_register(&imx6q_pinctrl_driver);
    +}
    +arch_initcall(imx6q_pinctrl_init);
    +
    +static void __exit imx6q_pinctrl_exit(void)
    +{
    + platform_driver_unregister(&imx6q_pinctrl_driver);
    +}
    +module_exit(imx6q_pinctrl_exit);
    +MODULE_AUTHOR("Dong Aisheng <dong.aisheng@linaro.org>");
    +MODULE_DESCRIPTION("Freescale IMX6Q pinctrl driver");
    +MODULE_LICENSE("GPL v2");
    --
    1.7.0.4



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      Last update: 2012-04-26 16:35    [W:0.363 / U:30.076 seconds]
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