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SubjectRe: [PATCH 06/12] perf/x86-ibs: Precise event sampling with IBS for AMD CPUs
On 14.04.12 12:22:10, Peter Zijlstra wrote:
> On Mon, 2012-04-02 at 20:19 +0200, Robert Richter wrote:
> > + * IbsOpCntCtl (bit 19) of IBS Execution Control Register (IbsOpCtl,
> > + * MSRC001_1033) is used to select either cycle or micro-ops counting
> > + * mode.
>
> Ah is that what it does.. the BKDG doesn't appear to say this.

"19 IbsOpCntCtl: periodic op counter count control. Revision B:
Reserved. Revision C: Read-write. Reset 0b. 1=Count dispatched ops
0=Count clock cycles."

It's here:

MSRC001_1033 IBS Execution Control Register (IbsOpCtl)
http://support.amd.com/us/Processor_TechDocs/31116.pdf

Ok, it might not be quite clear that "dispatched ops" is related to
EventSelect 0C1h Retired uops, but there is an exact mapping.

-Robert

--
Advanced Micro Devices, Inc.
Operating System Research Center



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