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SubjectRe: i915_driver_irq_handler: irq 42: nobody cared
On Tue, Apr 10, 2012 at 01:34:11PM -0700, Jesse Barnes wrote:
> On Tue, 10 Apr 2012 22:32:12 +0200
> Daniel Vetter <daniel@ffwll.ch> wrote:
>
> > On Tue, Apr 10, 2012 at 09:52:40PM +0200, Jiri Slaby wrote:
> > > Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort-
> > > <TAbort- <MAbort- >SERR- <PERR- INTx-
> > >
> > > I tried 3.2 and 3.3. Although the spurious interrupts were always
> > > there, they occurred with frequency lower by a magnitude (15 vs. 300
> > > after X starts). So I bisected that and it lead to a commit which
> > > fixes bad tiling for me:
> > > http://cgit.freedesktop.org/~ickle/linux-2.6/commit/?h=for-jiri&id=79710e6ccabdac80c65cd13b944695ecc3e42a9d
> >
> > Pipelined fencing is pretty much just broken and we'll completely rip it
> > out in 3.5. Does this also happen with 3.4-rc2?
>
> Does INTx- stay that way? Or does it frequently read INTx+ if you
> sample it a lot? If it stays as INTx-, then something other than the
> GPU is getting stuck (though it's possible this could be related to
> pipelined fencing, if the fences are programmed to point at some funky
> memory space).

Shot in the dark, let's disable msi a bit. Can you try the below patch?


diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 785f67f..249d5fe 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -2071,6 +2071,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
else if (IS_GEN5(dev))
i915_ironlake_get_mem_freq(dev);

+#if 0
/* On the 945G/GM, the chipset reports the MSI capability on the
* integrated graphics even though the support isn't actually there
* according to the published specs. It doesn't appear to function
@@ -2084,6 +2085,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
*/
if (!IS_I945G(dev) && !IS_I945GM(dev))
pci_enable_msi(dev->pdev);
+#endif

spin_lock_init(&dev_priv->gt_lock);
spin_lock_init(&dev_priv->irq_lock);
--
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

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