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SubjectRe: i915_driver_irq_handler: irq 42: nobody cared
On Tue, 10 Apr 2012 22:32:12 +0200
Daniel Vetter <> wrote:

> On Tue, Apr 10, 2012 at 09:52:40PM +0200, Jiri Slaby wrote:
> > Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort-
> > <TAbort- <MAbort- >SERR- <PERR- INTx-
> >
> > I tried 3.2 and 3.3. Although the spurious interrupts were always
> > there, they occurred with frequency lower by a magnitude (15 vs. 300
> > after X starts). So I bisected that and it lead to a commit which
> > fixes bad tiling for me:
> >
> Pipelined fencing is pretty much just broken and we'll completely rip it
> out in 3.5. Does this also happen with 3.4-rc2?

Does INTx- stay that way? Or does it frequently read INTx+ if you
sample it a lot? If it stays as INTx-, then something other than the
GPU is getting stuck (though it's possible this could be related to
pipelined fencing, if the fences are programmed to point at some funky
memory space).

Jesse Barnes, Intel Open Source Technology Center
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