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SubjectRe: [PATCH] Clear previous interrupts after fifo is disabled
On Thu, Mar 8, 2012 at 7:49 PM, Greg Kroah-Hartman
<> wrote:
> On Mon, Feb 27, 2012 at 06:30:20PM +0900, Chanho Min wrote:
>> This is another workaroud of  ''
>> with additional analysis.Bootloader can transfer control to kernel and
>> there are some pending interrupts. In this case, RXFE of the flag
>> register is set by clearing FEN(LCRH) even if rx data remains in the
>> fifo. It seems that the fifo's status is initiailized. Interrupt
>> handler can not get any data from data register because of the below
>> break condtion.
>> pl011_fifo_to_tty
>>  while (max_count--) {
>>    if (status & UART01x_FR_RXFE)
>>       break;
> This patch never seemed to be agreed on, so I'm not taking it.
> Can someone, if this is still needed, and everyone agrees on how to
> solve it, please send me the needed fix?

To me it seems Russell's patch solves part of the problem,
and Jong-Sung Kim's patch on top of that solves the entire
problem, but Chanho need to come back and tell whether
this is the case in practice.

Linus Walleij
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