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    Subject[tip:perf/hw-branch-sampling] perf/x86: Disable LBR support for older Intel Atom processors
    Commit-ID:  88c9a65e13f393fd60d8b9e9c659a34f9e39967d
    Gitweb: http://git.kernel.org/tip/88c9a65e13f393fd60d8b9e9c659a34f9e39967d
    Author: Stephane Eranian <eranian@google.com>
    AuthorDate: Thu, 9 Feb 2012 23:20:56 +0100
    Committer: Ingo Molnar <mingo@elte.hu>
    CommitDate: Mon, 5 Mar 2012 14:55:41 +0100

    perf/x86: Disable LBR support for older Intel Atom processors

    The patch adds a restriction for Intel Atom LBR support. Only
    steppings 10 (PineView) and more recent are supported. Older models
    do not have a functional LBR. Their LBR does not freeze on PMU
    interrupt which makes LBR unusable in the context of perf_events.

    Signed-off-by: Stephane Eranian <eranian@google.com>
    Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
    Link: http://lkml.kernel.org/r/1328826068-11713-7-git-send-email-eranian@google.com
    Signed-off-by: Ingo Molnar <mingo@elte.hu>
    ---
    arch/x86/kernel/cpu/perf_event_intel_lbr.c | 10 ++++++++++
    1 files changed, 10 insertions(+), 0 deletions(-)

    diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
    index e54a063..07f0ff8 100644
    --- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
    +++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
    @@ -315,6 +315,16 @@ void intel_pmu_lbr_init_snb(void)
    /* atom */
    void intel_pmu_lbr_init_atom(void)
    {
    + /*
    + * only models starting at stepping 10 seems
    + * to have an operational LBR which can freeze
    + * on PMU interrupt
    + */
    + if (boot_cpu_data.x86_mask < 10) {
    + pr_cont("LBR disabled due to erratum");
    + return;
    + }
    +
    x86_pmu.lbr_nr = 8;
    x86_pmu.lbr_tos = MSR_LBR_TOS;
    x86_pmu.lbr_from = MSR_LBR_CORE_FROM;

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