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SubjectRE: [PATCH] Clear previous interrupts after fifo is disabled
> -----Original Message-----
> From: Chanho Min []
> Sent: Monday, February 27, 2012 6:30 PM
> To: Russell King; Alan Cox; Greg Kroah-Hartman; Linus Walleij; Shreshtha
> Kumar Sahu; Kim, Jong-Sung
> Cc:;
> Subject: [PATCH] Clear previous interrupts after fifo is disabled
> This is another workaroud of ''
> with additional analysis.Bootloader can transfer control to kernel and
> are some pending interrupts. In this case, RXFE of the flag register is
> by clearing FEN(LCRH) even if rx data remains in the fifo. It seems that
> fifo's status is initiailized. Interrupt handler can not get any data from
> data register because of the below break condtion.
> pl011_fifo_to_tty
> while (max_count--) {
> if (status & UART01x_FR_RXFE)
> break;
> Then, Rx interrupt is never cleared. cpu is looping in ISR. System is
> If we don't guarantee that no interrupt is pended until fifo is disabled
> calling 'writew(0, uap->port.membase + uap->lcrh_rx)', this misbehave of
> interrupt handelr can be occurred. So, All pending interrupts should be
> cleared just after fifo is disabled under the protection from interrupt.
> Also,'clear error interrupts' routine can be removed becuase all
> are cleared before.
> Signed-off-by: Chanho Min <>

May I suggest another approach at this point? The problematic condition you
reported could be considered as an exceptional Rx interrupt status. So, we
can handle it in the Rx ISR. Simply:

diff --git a/drivers/tty/serial/amba-pl011.c
index 6800f5f..5b5358705 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -224,6 +224,10 @@ static int pl011_fifo_to_tty(struct uart_amba_port
uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);

+ /* RXIS but RXFE? Just clear the interrupt */
+ if(unlikely(fifotaken == 0))
+ writew(UART011_RXIS, uap->port.membase + UART01x_ICR);
return fifotaken;

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