Messages in this thread | | | Subject | Re: x2APIC and many-APIC systems... | From | Suresh Siddha <> | Date | Tue, 13 Mar 2012 16:16:29 -0700 |
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On Tue, 2012-03-13 at 15:58 -0700, Yinghai Lu wrote: > On Tue, Mar 13, 2012 at 2:29 AM, Daniel J Blueman > <daniel@numascale-asia.com> wrote: > > Ingo, Suresh, > > > > Commit a35fd28256e7736cc84af8931a16224f0bfaaf6c prevents x2APIC structures > > being used from the ACPI MADT if the cores don't advertise the x2APIC > > feature. Commit c284b42abadbb22083bfde24d308899c08d44ffa prevents onlining > > cores with APIC ID >255 in non-x2APIC mode. Since NumaChip/NumaConnect uses > > x2APIC structures to describe non-x2APIC systems (AMD Opteron) with lots of > > APICs, we thus now can't boot all the cores. > > > > We are able to set the x2APIC bit in the processor feature flags, so get > > caught by the second patch. Is there an appropriate approach to use in these > > circumstances? Otherwise, would a patch that separates the APIC ID handover > > and future x2APIC MSR access be appropriate? > > > > add is_apicid_valid() in struct apic?
Yes, we can generalize that and move into the apicdriver. Daniel, will you be able to prepare such a patch?
thanks, suresh
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