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SubjectRe: [PATCH 02/15] PCI: Add iobusn_resource
On Fri, Feb 3, 2012 at 6:30 PM, Yinghai Lu <> wrote:
> On Fri, Feb 3, 2012 at 3:38 PM, Benjamin Herrenschmidt
> <> wrote:
>> On Fri, 2012-02-03 at 08:36 -0800, Bjorn Helgaas wrote:
>>> On Wed, Feb 1, 2012 at 2:43 PM, Yinghai Lu <> wrote:
>>> > also add busn_res into struct pci_bus.
>>> >
>>> > will use them to have bus number resource tree.

>> To be honest that whole business with bus numbers in struct resource
>> seems like gratuituous bloat & over engineering to me ...
> ah, i thought it is simple enough, and should be done before already.
>> Does it actually solve a specific problem or serve a purpose ?
> very beginning is for one IBM x3950...
> ++max searching valid bus number range is out of boundary of peer root
> bus range.
> later, found the code could help: pcie hotplug, pci bus rescan and
> even remove some hacks for/from cardbus field.
> now with this patchset (+ one patch that is not sent out yet), I could
> even use setpci/pci rescan to move pci bus around.

The current bus number allocation in pci_scan_bridge() is very simple
-- we just add one to the highest-numbered bridge we've seen. That
works in many cases, but it means any holes in the range of used bus
numbers are just wasted.

Here's a case I tripped over where the current scheme fails. The
machine boots with bridge 00:03.0 to [bus 05-19]. Now we hot-add a
hierarchy that is currently configured like this:

05:00.0 bridge to [bus 06-1e]
06:05.0 bridge to [bus 1c]
06:06.0 bridge to [bus 1d]
1c:00.0 NIC0
1d:00.0 NIC1

[bus 1a-1e] is inaccessible because the 00:03.0 aperture only includes
[bus 05-19]. There's plenty of space to reconfigure the hierarchy,
e.g., to make 05:00.0 lead to [bus 06-19], 06:05.0 lead to [bus 18],
and 06:06.0 lead to [bus 19]. But we aren't smart enough to do that.

So I think it's important to improve bus number allocation to make hot
plug more robust, but I don't think the current series is
understandable or maintainable yet.


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