[lkml]   [2012]   [Feb]   [13]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
    SubjectRe: Regulator enable/disable delay based on board design: How to handle?
    On Mon, Feb 13, 2012 at 02:48:18PM +0530, Laxman Dewangan wrote:

    > We observed that some of the rail enable/disable settling time
    > depends on the board design specially based on external capacitor
    > connected on
    > rails. This is observed mainly on VBUS regulator rail where
    > difference on the capacitance value which is connected on rail makes
    > the on/off
    > time to vary.

    Usually this would be handled via regulator driver platform data as the
    regulator will typically be designed with particular external components
    in mind and (especially in the case of DCDC convertors) may need to be
    configured differently depending on the choice of passive components.
    Many regulators also have some software control for the ramp rate,
    mainly intended to limit inrush currents on system startup, which can be
    varied at runtime if desired.
    [unhandled content-type:application/pgp-signature]
     \ /
      Last update: 2012-02-13 17:39    [W:0.018 / U:5.520 seconds]
    ©2003-2016 Jasper Spaans. hosted at Digital OceanAdvertise on this site