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    Subject[PATCH 170/241] sparc64: Fix bit twiddling in sparc_pmu_enable_event().
    Date
    3.5.7.2 -stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: "David S. Miller" <davem@davemloft.net>

    commit e793d8c6740f8fe704fa216e95685f4d92c4c4b9 upstream.

    There was a serious disconnect in the logic happening in
    sparc_pmu_disable_event() vs. sparc_pmu_enable_event().

    Event disable is implemented by programming a NOP event into the PCR.

    However, event enable was not reversing this operation. Instead, it
    was setting the User/Priv/Hypervisor trace enable bits.

    That's not sparc_pmu_enable_event()'s job, that's what
    sparc_pmu_enable() and sparc_pmu_disable() do .

    The intent of sparc_pmu_enable_event() is clear, since it first clear
    out the event type encoding field. So fix this by OR'ing in the event
    encoding rather than the trace enable bits.

    Signed-off-by: David S. Miller <davem@davemloft.net>
    Signed-off-by: Herton Ronaldo Krzesinski <herton.krzesinski@canonical.com>
    ---
    arch/sparc/kernel/perf_event.c | 6 ++++--
    1 file changed, 4 insertions(+), 2 deletions(-)

    diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c
    index b0cce26..ac18037 100644
    --- a/arch/sparc/kernel/perf_event.c
    +++ b/arch/sparc/kernel/perf_event.c
    @@ -557,11 +557,13 @@ static u64 nop_for_index(int idx)

    static inline void sparc_pmu_enable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx)
    {
    - u64 val, mask = mask_for_index(idx);
    + u64 enc, val, mask = mask_for_index(idx);
    +
    + enc = perf_event_get_enc(cpuc->events[idx]);

    val = cpuc->pcr;
    val &= ~mask;
    - val |= hwc->config;
    + val |= event_encoding(enc, idx);
    cpuc->pcr = val;

    pcr_ops->write(cpuc->pcr);
    --
    1.7.9.5


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