Messages in this thread | | | Date | Mon, 12 Nov 2012 15:36:30 +0100 | From | Robert Richter <> | Subject | Re: [PATCH 0/4] perf, amd: Enable AMD family 15h northbridge counters |
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On 11.11.12 19:17:07, Stephane Eranian wrote: > On Sat, Nov 10, 2012 at 12:50 PM, Robert Richter <rric@kernel.org> wrote: > > Peter's main concerns were that my patch set is not in the > > Intel-uncore style. I started reworking this but was not able to > > finish my work. This concerns still exist. > > > That was my concern too. I don't recall exactly why it could not > be totally disconnected from the core PMU. I think hardware-wise, > it was possible. Could you refresh my memory?
Current implementation only allows the use of a single x86 pmu. Multiple instances of x86 pmus in a system like an additional pmu for nb counters requires a complete rework. You need to remove global variables and extend function interfaces by arguments pointing to a struct x86_pmu. All this without adding overhead (e.g. pointer chasing) compared to the existing code.
This is also the reason why the intel-uncore implemenation is basically a copy-and-paste of generic x86 pmu code plus uncore specific changes.
Avoiding code cuplication and a complex rework were the reasons for simply extending the family 10h implementation to also support family 15h nb counters. This seemed to me the best approach that time.
-Robert
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