| From | Mark Langsdorf <> | Subject | [PATCH 2/6] clk, highbank: remove non-bypass reset mode | Date | Tue, 30 Oct 2012 16:04:12 -0500 |
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The highbank clock will glitch if the clock rate is reset without relocking the PLL. Remove the option to attempt reseting without relocking.
Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: Rob Herring <rob.herring@calxeda.com> --- drivers/clk/clk-highbank.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-highbank.c b/drivers/clk/clk-highbank.c index 52fecad..4f50c42 100644 --- a/drivers/clk/clk-highbank.c +++ b/drivers/clk/clk-highbank.c @@ -171,7 +171,8 @@ static int clk_pll_set_rate(struct clk_hw *hwclk, unsigned long rate, writel(reg | HB_PLL_RESET, hbclk->reg); reg &= ~(HB_PLL_DIVF_MASK | HB_PLL_DIVQ_MASK); - reg |= (divf << HB_PLL_DIVF_SHIFT) | (divq << HB_PLL_DIVQ_SHIFT); + reg |= (divf << HB_PLL_DIVF_SHIFT) | + (divq << HB_PLL_DIVQ_SHIFT); writel(reg | HB_PLL_RESET, hbclk->reg); writel(reg, hbclk->reg); @@ -182,8 +183,10 @@ static int clk_pll_set_rate(struct clk_hw *hwclk, unsigned long rate, reg |= HB_PLL_EXT_ENA; reg &= ~HB_PLL_EXT_BYPASS; } else { + writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg); reg &= ~HB_PLL_DIVQ_MASK; reg |= divq << HB_PLL_DIVQ_SHIFT; + writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg); } writel(reg, hbclk->reg); -- 1.7.11.7
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