Messages in this thread | | | Date | Fri, 26 Oct 2012 15:52:51 +0200 | From | Roland Stigge <> | Subject | Re: [PATCH 2/2] ARM: mach-imx: CAN clock fix for i.MX53 |
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On 10/26/2012 01:05 PM, Roland Stigge wrote: > On 10/26/2012 12:30 PM, Marc Kleine-Budde wrote: >>>>> + clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", >>>>> "can_sel", MXC_CCM_CCGR4, 6); + clk[can1_ipg_gate] = >>>>> imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR4, 8); + >>>>> clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", >>>>> "can_sel", MXC_CCM_CCGR4, 6); + clk[can2_ipg_gate] = >>>>> imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 8); >>>> >>>> This doesn't. >>> >>> This may be right, but unfortunately, since the introduction of >>> your can1 + can2 clocking change, the first block stopped working >>> for me. >> >> You are effectively using can2's clock for can1. Are you sure you >> haven't mixed up can1 and can2? > > Just using the above patch and patch 1/2 from this series (missing can > pinmuxing), doing like this in custom .dts: > > + can1: can@53fc8000 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_can1_1>; > + clock-frequency = <66500000>;
That was the problem, since in flexcan.c probe():
if (pdev->dev.of_node) of_property_read_u32(pdev->dev.of_node, "clock-frequency", &clock_freq);
if (!clock_freq) { clk_ipg = devm_clk_get(&pdev->dev, "ipg"); if (IS_ERR(clk_ipg)) { dev_err(&pdev->dev, "no ipg clock defined\n"); err = PTR_ERR(clk_ipg); goto failed_clock; } clock_freq = clk_get_rate(clk_ipg);
clk_per = devm_clk_get(&pdev->dev, "per"); if (IS_ERR(clk_per)) { dev_err(&pdev->dev, "no per clock defined\n"); err = PTR_ERR(clk_per); goto failed_clock; } }
Sorry for the noise.
The other patches are still current.
Thanks,
Roland
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