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    Subject[PATCH 06/13] perf_events: disable LBR support for older Intel Atom processors (v3)
    Date
    The patch adds a restriction for Intel Atom LBR support. Only
    steppings 10 (PineView) and more recent are supported. Older models,
    do not have a functional LBR. Their LBR does not freeze on PMU interrupt
    which makes LBR unusable in the context of perf_events.

    Signed-off-by: Stephane Eranian <eranian@google.com>
    ---
    arch/x86/kernel/cpu/perf_event_intel_lbr.c | 10 ++++++++++
    1 files changed, 10 insertions(+), 0 deletions(-)

    diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
    index 8a1eb6c..e2b7094 100644
    --- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
    +++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
    @@ -313,6 +313,16 @@ void intel_pmu_lbr_init_snb(void)
    /* atom */
    void intel_pmu_lbr_init_atom(void)
    {
    + /*
    + * only models starting at stepping 10 seems
    + * to have an operational LBR which can freeze
    + * on PMU interrupt
    + */
    + if (boot_cpu_data.x86_mask < 10) {
    + pr_cont("LBR disabled due to erratum");
    + return;
    + }
    +
    x86_pmu.lbr_nr = 8;
    x86_pmu.lbr_tos = MSR_LBR_TOS;
    x86_pmu.lbr_from = MSR_LBR_CORE_FROM;
    --
    1.7.1


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