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    Subject[51/75] sparc64: Fix MSIQ HV call ordering in pci_sun4v_msiq_build_irq().
    3.1-stable review patch.  If anyone has any objections, please let me know.

    ------------------


    From: "David S. Miller" <davem@davemloft.net>

    [ Upstream commit 7cc8583372a21d98a23b703ad96cab03180b5030 ]

    This silently was working for many years and stopped working on
    Niagara-T3 machines.

    We need to set the MSIQ to VALID before we can set it's state to IDLE.

    On Niagara-T3, setting the state to IDLE first was causing HV_EINVAL
    errors. The hypervisor documentation says, rather ambiguously, that
    the MSIQ must be "initialized" before one can set the state.

    I previously understood this to mean merely that a successful setconf()
    operation has been performed on the MSIQ, which we have done at this
    point. But it seems to also mean that it has been set VALID too.

    Signed-off-by: David S. Miller <davem@davemloft.net>
    Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
    ---
    arch/sparc/kernel/pci_sun4v.c | 4 ++--
    1 file changed, 2 insertions(+), 2 deletions(-)

    --- a/arch/sparc/kernel/pci_sun4v.c
    +++ b/arch/sparc/kernel/pci_sun4v.c
    @@ -848,10 +848,10 @@ static int pci_sun4v_msiq_build_irq(stru
    if (!irq)
    return -ENOMEM;

    - if (pci_sun4v_msiq_setstate(pbm->devhandle, msiqid, HV_MSIQSTATE_IDLE))
    - return -EINVAL;
    if (pci_sun4v_msiq_setvalid(pbm->devhandle, msiqid, HV_MSIQ_VALID))
    return -EINVAL;
    + if (pci_sun4v_msiq_setstate(pbm->devhandle, msiqid, HV_MSIQSTATE_IDLE))
    + return -EINVAL;

    return irq;
    }



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