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Subject[PATCH 3/4] ARM: tegra: Switch to new pinctrl driver
Date
* Rename old pinmux and new pinctrl platform driver and DT match table
entries, so the new driver gets instantiated.
* Re-write board-pinmux.c, so that it uses pinctrl APIs to configura the
pinmux.
* Re-write board-*-pinmux.c so that the pinmux configuration tables are
in pinctrl format.

Ventana's pin mux table needed some edits on top of the basic format
conversion, since some mux options that were previously marked as
reserved are now valid in the new pinctrl driver. Attempting to use the
old reserved names will result in a failure. Specifically, groups lpw0,
lpw2, lsc1, lsck, and lsda were changed from function rsvd4 to displaya,
and group pta was changed from function rsvd2 to hdmi.

All boards' pin mux tables needed some edits on top of the based format
conversion, since function i2c was split into i2c1 (first general I2C
controller) and i2cp (power I2C controller) to better align function
definitions with HW blocks.

Due to the split of mux tables into pure mux and pull/tristate tables,
many entries in the separate Seaboard/Ventana tables could be merged
into the common table, since the entries differed only in the portion
in one of the tables, not both.

Most pin groups allow configuration of mux, tri-state, and pull. However,
some don't allow pull configuration, which is instead configured by new
groups that only allow pull configuration. This is a reflection of the
true HW capabilities, which weren't fully represented by the old pinmux
driver. This required adding new pull table entries for those new groups,
and setting many other entries' pull configuration to
TEGRA_PINCONFIG_DONT_SET.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
arch/arm/mach-tegra/board-harmony-pinmux.c | 362 ++++++++++++++-------
arch/arm/mach-tegra/board-paz00-pinmux.c | 362 ++++++++++++++-------
arch/arm/mach-tegra/board-pinmux.c | 62 ++++-
arch/arm/mach-tegra/board-pinmux.h | 39 ++-
arch/arm/mach-tegra/board-seaboard-pinmux.c | 442 ++++++++++++++++---------
arch/arm/mach-tegra/board-trimslice-pinmux.c | 366 ++++++++++++++--------
arch/arm/mach-tegra/pinmux.c | 6 +-
drivers/pinctrl/pinctrl-tegra.c | 6 +-
8 files changed, 1095 insertions(+), 550 deletions(-)

diff --git a/arch/arm/mach-tegra/board-harmony-pinmux.c b/arch/arm/mach-tegra/board-harmony-pinmux.c
index 465808c..9788fd0 100644
--- a/arch/arm/mach-tegra/board-harmony-pinmux.c
+++ b/arch/arm/mach-tegra/board-harmony-pinmux.c
@@ -2,6 +2,7 @@
* arch/arm/mach-tegra/board-harmony-pinmux.c
*
* Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -15,133 +16,244 @@
*/

#include <linux/kernel.h>
-#include <linux/gpio.h>
-#include <linux/of.h>
-
-#include <mach/pinmux.h>
-#include <mach/pinmux-tegra20.h>

#include "gpio-names.h"
#include "board-harmony.h"
#include "board-pinmux.h"

-static struct tegra_pingroup_config harmony_pinmux[] = {
- {TEGRA_PINGROUP_ATA, TEGRA_MUX_IDE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_DDC, TEGRA_MUX_I2C2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_DTA, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_DTB, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_DTC, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_DTD, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_DTE, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_GMB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_GMC, TEGRA_MUX_UARTD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_GMD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_GME, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_GPU, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_KBCB, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_KBCD, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LCSN, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LDC, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LM0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LM1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LPW0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LPW1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LPW2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LSC1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LSCK, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LSDA, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LSDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LVP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_OWC, TEGRA_MUX_RSVD2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_PTA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_SDB, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SDC, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_SDD, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SPDI, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_UAD, TEGRA_MUX_IRDA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+static struct pinmux_map harmony_map[] = {
+ TEGRA_PINMUX_MAP("ata", "ide"),
+ TEGRA_PINMUX_MAP("atb", "sdio4"),
+ TEGRA_PINMUX_MAP("atc", "nand"),
+ TEGRA_PINMUX_MAP("atd", "gmi"),
+ TEGRA_PINMUX_MAP("ate", "gmi"),
+ TEGRA_PINMUX_MAP("cdev1", "plla_out"),
+ TEGRA_PINMUX_MAP("cdev2", "pllp_out4"),
+ TEGRA_PINMUX_MAP("crtp", "crt"),
+ TEGRA_PINMUX_MAP("csus", "vi_sensor_clk"),
+ TEGRA_PINMUX_MAP("dap1", "dap1"),
+ TEGRA_PINMUX_MAP("dap2", "dap2"),
+ TEGRA_PINMUX_MAP("dap3", "dap3"),
+ TEGRA_PINMUX_MAP("dap4", "dap4"),
+ TEGRA_PINMUX_MAP("ddc", "i2c2"),
+ TEGRA_PINMUX_MAP("dta", "sdio2"),
+ TEGRA_PINMUX_MAP("dtb", "rsvd1"),
+ TEGRA_PINMUX_MAP("dtc", "rsvd1"),
+ TEGRA_PINMUX_MAP("dtd", "sdio2"),
+ TEGRA_PINMUX_MAP("dte", "rsvd1"),
+ TEGRA_PINMUX_MAP("dtf", "i2c3"),
+ TEGRA_PINMUX_MAP("gma", "sdio4"),
+ TEGRA_PINMUX_MAP("gmb", "gmi"),
+ TEGRA_PINMUX_MAP("gmc", "uartd"),
+ TEGRA_PINMUX_MAP("gmd", "gmi"),
+ TEGRA_PINMUX_MAP("gme", "sdio4"),
+ TEGRA_PINMUX_MAP("gpu", "gmi"),
+ TEGRA_PINMUX_MAP("gpu7", "rtck"),
+ TEGRA_PINMUX_MAP("gpv", "pcie"),
+ TEGRA_PINMUX_MAP("hdint", "hdmi"),
+ TEGRA_PINMUX_MAP("i2cp", "i2cp"),
+ TEGRA_PINMUX_MAP("irrx", "uarta"),
+ TEGRA_PINMUX_MAP("irtx", "uarta"),
+ TEGRA_PINMUX_MAP("kbca", "kbc"),
+ TEGRA_PINMUX_MAP("kbcb", "kbc"),
+ TEGRA_PINMUX_MAP("kbcc", "kbc"),
+ TEGRA_PINMUX_MAP("kbcd", "kbc"),
+ TEGRA_PINMUX_MAP("kbce", "kbc"),
+ TEGRA_PINMUX_MAP("kbcf", "kbc"),
+ TEGRA_PINMUX_MAP("lcsn", "displaya"),
+ TEGRA_PINMUX_MAP("ld0", "displaya"),
+ TEGRA_PINMUX_MAP("ld1", "displaya"),
+ TEGRA_PINMUX_MAP("ld2", "displaya"),
+ TEGRA_PINMUX_MAP("ld3", "displaya"),
+ TEGRA_PINMUX_MAP("ld4", "displaya"),
+ TEGRA_PINMUX_MAP("ld5", "displaya"),
+ TEGRA_PINMUX_MAP("ld6", "displaya"),
+ TEGRA_PINMUX_MAP("ld7", "displaya"),
+ TEGRA_PINMUX_MAP("ld8", "displaya"),
+ TEGRA_PINMUX_MAP("ld9", "displaya"),
+ TEGRA_PINMUX_MAP("ld10", "displaya"),
+ TEGRA_PINMUX_MAP("ld11", "displaya"),
+ TEGRA_PINMUX_MAP("ld12", "displaya"),
+ TEGRA_PINMUX_MAP("ld13", "displaya"),
+ TEGRA_PINMUX_MAP("ld14", "displaya"),
+ TEGRA_PINMUX_MAP("ld15", "displaya"),
+ TEGRA_PINMUX_MAP("ld16", "displaya"),
+ TEGRA_PINMUX_MAP("ld17", "displaya"),
+ TEGRA_PINMUX_MAP("ldc", "displaya"),
+ TEGRA_PINMUX_MAP("ldi", "displaya"),
+ TEGRA_PINMUX_MAP("lhp0", "displaya"),
+ TEGRA_PINMUX_MAP("lhp1", "displaya"),
+ TEGRA_PINMUX_MAP("lhp2", "displaya"),
+ TEGRA_PINMUX_MAP("lhs", "displaya"),
+ TEGRA_PINMUX_MAP("lm0", "displaya"),
+ TEGRA_PINMUX_MAP("lm1", "displaya"),
+ TEGRA_PINMUX_MAP("lpp", "displaya"),
+ TEGRA_PINMUX_MAP("lpw0", "displaya"),
+ TEGRA_PINMUX_MAP("lpw1", "displaya"),
+ TEGRA_PINMUX_MAP("lpw2", "displaya"),
+ TEGRA_PINMUX_MAP("lsc0", "displaya"),
+ TEGRA_PINMUX_MAP("lsc1", "displaya"),
+ TEGRA_PINMUX_MAP("lsck", "displaya"),
+ TEGRA_PINMUX_MAP("lsda", "displaya"),
+ TEGRA_PINMUX_MAP("lsdi", "displaya"),
+ TEGRA_PINMUX_MAP("lspi", "displaya"),
+ TEGRA_PINMUX_MAP("lvp0", "displaya"),
+ TEGRA_PINMUX_MAP("lvp1", "displaya"),
+ TEGRA_PINMUX_MAP("lvs", "displaya"),
+ TEGRA_PINMUX_MAP("owc", "rsvd2"),
+ TEGRA_PINMUX_MAP("pmc", "pwr_on"),
+ TEGRA_PINMUX_MAP("pta", "hdmi"),
+ TEGRA_PINMUX_MAP("rm", "i2c1"),
+ TEGRA_PINMUX_MAP("sdb", "pwm"),
+ TEGRA_PINMUX_MAP("sdc", "pwm"),
+ TEGRA_PINMUX_MAP("sdd", "pwm"),
+ TEGRA_PINMUX_MAP("sdio1", "sdio1"),
+ TEGRA_PINMUX_MAP("slxa", "pcie"),
+ TEGRA_PINMUX_MAP("slxc", "spdif"),
+ TEGRA_PINMUX_MAP("slxd", "spdif"),
+ TEGRA_PINMUX_MAP("slxk", "pcie"),
+ TEGRA_PINMUX_MAP("spdi", "rsvd2"),
+ TEGRA_PINMUX_MAP("spdo", "rsvd2"),
+ TEGRA_PINMUX_MAP("spia", "gmi"),
+ TEGRA_PINMUX_MAP("spib", "gmi"),
+ TEGRA_PINMUX_MAP("spic", "gmi"),
+ TEGRA_PINMUX_MAP("spid", "spi1"),
+ TEGRA_PINMUX_MAP("spie", "spi1"),
+ TEGRA_PINMUX_MAP("spif", "spi1"),
+ TEGRA_PINMUX_MAP("spig", "spi2_alt"),
+ TEGRA_PINMUX_MAP("spih", "spi2_alt"),
+ TEGRA_PINMUX_MAP("uaa", "ulpi"),
+ TEGRA_PINMUX_MAP("uab", "ulpi"),
+ TEGRA_PINMUX_MAP("uac", "rsvd2"),
+ TEGRA_PINMUX_MAP("uad", "irda"),
+ TEGRA_PINMUX_MAP("uca", "uartc"),
+ TEGRA_PINMUX_MAP("ucb", "uartc"),
+ TEGRA_PINMUX_MAP("uda", "ulpi"),
+};
+
+struct tegra_board_pinmux_pg_conf harmony_pg[] = {
+ {"ata", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"atb", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"atc", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"atd", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"ate", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"cdev1", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"cdev2", TEGRA_PINCONFIG_PULL_DOWN, TEGRA_PINCONFIG_TRISTATE},
+ {"crtp", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"csus", TEGRA_PINCONFIG_PULL_DOWN, TEGRA_PINCONFIG_TRISTATE},
+ {"dap1", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"dap2", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"dap3", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"dap4", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"ddc", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DRIVEN},
+ {"dta", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DRIVEN},
+ {"dtb", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"dtc", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"dtd", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DRIVEN},
+ {"dte", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"dtf", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"gma", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"gmb", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"gmc", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"gmd", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"gme", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"gpu", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"gpu7", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"gpv", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"hdint", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"i2cp", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"irrx", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"irtx", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"kbca", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DRIVEN},
+ {"kbcb", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DRIVEN},
+ {"kbcc", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DRIVEN},
+ {"kbcd", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DRIVEN},
+ {"kbce", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DRIVEN},
+ {"kbcf", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DRIVEN},
+ {"lcsn", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"ld0", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld1", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld2", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld3", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld4", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld5", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld6", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld7", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld8", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld9", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld10", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld11", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld12", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld13", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld14", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld15", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld16", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld17", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ldc", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"ldi", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lhp0", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lhp1", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lhp2", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lhs", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lm0", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lm1", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"lpp", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lpw0", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lpw1", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"lpw2", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lsc0", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lsc1", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"lsck", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"lsda", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"lsdi", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"lspi", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lvp0", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"lvp1", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lvs", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"owc", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"pmc", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"pta", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"rm", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"sdb", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"sdc", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DRIVEN},
+ {"sdd", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"sdio1", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"slxa", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"slxc", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"slxd", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"slxk", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"spdi", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"spdo", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"spia", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"spib", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"spic", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"spid", TEGRA_PINCONFIG_PULL_DOWN, TEGRA_PINCONFIG_TRISTATE},
+ {"spie", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"spif", TEGRA_PINCONFIG_PULL_DOWN, TEGRA_PINCONFIG_TRISTATE},
+ {"spig", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"spih", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"uaa", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"uab", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"uac", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"uad", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"uca", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"ucb", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"uda", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"ck32", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"ddrc", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"pmca", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"pmcb", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"pmcc", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"pmcd", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"pmce", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"xm2c", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"xm2d", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"ls", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DONT_SET},
+ {"lc", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DONT_SET},
+ {"ld17_0", TEGRA_PINCONFIG_PULL_DOWN, TEGRA_PINCONFIG_DONT_SET},
+ {"ld19_18", TEGRA_PINCONFIG_PULL_DOWN, TEGRA_PINCONFIG_DONT_SET},
+ {"ld21_20", TEGRA_PINCONFIG_PULL_DOWN, TEGRA_PINCONFIG_DONT_SET},
+ {"ld23_22", TEGRA_PINCONFIG_PULL_DOWN, TEGRA_PINCONFIG_DONT_SET},
};

static struct tegra_gpio_table gpio_table[] = {
@@ -158,8 +270,10 @@ static struct tegra_gpio_table gpio_table[] = {
};

static struct tegra_board_pinmux_conf conf = {
- .pgs = harmony_pinmux,
- .pg_count = ARRAY_SIZE(harmony_pinmux),
+ .maps = harmony_map,
+ .map_count = ARRAY_SIZE(harmony_map),
+ .pgs = harmony_pg,
+ .pg_count = ARRAY_SIZE(harmony_pg),
.gpios = gpio_table,
.gpio_count = ARRAY_SIZE(gpio_table),
};
diff --git a/arch/arm/mach-tegra/board-paz00-pinmux.c b/arch/arm/mach-tegra/board-paz00-pinmux.c
index c775572..0a93f1b 100644
--- a/arch/arm/mach-tegra/board-paz00-pinmux.c
+++ b/arch/arm/mach-tegra/board-paz00-pinmux.c
@@ -2,6 +2,7 @@
* arch/arm/mach-tegra/board-paz00-pinmux.c
*
* Copyright (C) 2010 Marc Dietrich <marvin24@gmx.de>
+ * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -15,133 +16,244 @@
*/

#include <linux/kernel.h>
-#include <linux/gpio.h>
-#include <linux/of.h>
-
-#include <mach/pinmux.h>
-#include <mach/pinmux-tegra20.h>

#include "gpio-names.h"
#include "board-paz00.h"
#include "board-pinmux.h"

-static struct tegra_pingroup_config paz00_pinmux[] = {
- {TEGRA_PINGROUP_ATA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_ATC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_CSUS, TEGRA_MUX_PLLC_OUT1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_DAP2, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_DDC, TEGRA_MUX_I2C2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_DTA, TEGRA_MUX_RSVD1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_DTB, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_DTC, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_DTD, TEGRA_MUX_RSVD1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_DTE, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_GMB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_GMC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_GMD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_GME, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_GPU, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_KBCB, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_KBCD, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LCSN, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LDC, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LM0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LM1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LPW0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LPW1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LPW2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LSC1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LSCK, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LSDA, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LSDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LVP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_OWC, TEGRA_MUX_OWR, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_PTA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_SDB, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SDC, TEGRA_MUX_TWC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SDD, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPI4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPI4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_SPDI, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_SPID, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SPIE, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SPIF, TEGRA_MUX_RSVD4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_UAD, TEGRA_MUX_SPDIF, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+static struct pinmux_map paz00_map[] = {
+ TEGRA_PINMUX_MAP("ata", "gmi"),
+ TEGRA_PINMUX_MAP("atb", "sdio4"),
+ TEGRA_PINMUX_MAP("atc", "gmi"),
+ TEGRA_PINMUX_MAP("atd", "gmi"),
+ TEGRA_PINMUX_MAP("ate", "gmi"),
+ TEGRA_PINMUX_MAP("cdev1", "plla_out"),
+ TEGRA_PINMUX_MAP("cdev2", "pllp_out4"),
+ TEGRA_PINMUX_MAP("crtp", "crt"),
+ TEGRA_PINMUX_MAP("csus", "pllc_out1"),
+ TEGRA_PINMUX_MAP("dap1", "dap1"),
+ TEGRA_PINMUX_MAP("dap2", "gmi"),
+ TEGRA_PINMUX_MAP("dap3", "dap3"),
+ TEGRA_PINMUX_MAP("dap4", "dap4"),
+ TEGRA_PINMUX_MAP("ddc", "i2c2"),
+ TEGRA_PINMUX_MAP("dta", "rsvd1"),
+ TEGRA_PINMUX_MAP("dtb", "rsvd1"),
+ TEGRA_PINMUX_MAP("dtc", "rsvd1"),
+ TEGRA_PINMUX_MAP("dtd", "rsvd1"),
+ TEGRA_PINMUX_MAP("dte", "rsvd1"),
+ TEGRA_PINMUX_MAP("dtf", "i2c3"),
+ TEGRA_PINMUX_MAP("gma", "sdio4"),
+ TEGRA_PINMUX_MAP("gmb", "gmi"),
+ TEGRA_PINMUX_MAP("gmc", "gmi"),
+ TEGRA_PINMUX_MAP("gmd", "gmi"),
+ TEGRA_PINMUX_MAP("gme", "sdio4"),
+ TEGRA_PINMUX_MAP("gpu", "pwm"),
+ TEGRA_PINMUX_MAP("gpu7", "rtck"),
+ TEGRA_PINMUX_MAP("gpv", "pcie"),
+ TEGRA_PINMUX_MAP("hdint", "hdmi"),
+ TEGRA_PINMUX_MAP("i2cp", "i2cp"),
+ TEGRA_PINMUX_MAP("irrx", "uarta"),
+ TEGRA_PINMUX_MAP("irtx", "uarta"),
+ TEGRA_PINMUX_MAP("kbca", "kbc"),
+ TEGRA_PINMUX_MAP("kbcb", "sdio2"),
+ TEGRA_PINMUX_MAP("kbcc", "kbc"),
+ TEGRA_PINMUX_MAP("kbcd", "sdio2"),
+ TEGRA_PINMUX_MAP("kbce", "kbc"),
+ TEGRA_PINMUX_MAP("kbcf", "kbc"),
+ TEGRA_PINMUX_MAP("lcsn", "displaya"),
+ TEGRA_PINMUX_MAP("ld0", "displaya"),
+ TEGRA_PINMUX_MAP("ld1", "displaya"),
+ TEGRA_PINMUX_MAP("ld2", "displaya"),
+ TEGRA_PINMUX_MAP("ld3", "displaya"),
+ TEGRA_PINMUX_MAP("ld4", "displaya"),
+ TEGRA_PINMUX_MAP("ld5", "displaya"),
+ TEGRA_PINMUX_MAP("ld6", "displaya"),
+ TEGRA_PINMUX_MAP("ld7", "displaya"),
+ TEGRA_PINMUX_MAP("ld8", "displaya"),
+ TEGRA_PINMUX_MAP("ld9", "displaya"),
+ TEGRA_PINMUX_MAP("ld10", "displaya"),
+ TEGRA_PINMUX_MAP("ld11", "displaya"),
+ TEGRA_PINMUX_MAP("ld12", "displaya"),
+ TEGRA_PINMUX_MAP("ld13", "displaya"),
+ TEGRA_PINMUX_MAP("ld14", "displaya"),
+ TEGRA_PINMUX_MAP("ld15", "displaya"),
+ TEGRA_PINMUX_MAP("ld16", "displaya"),
+ TEGRA_PINMUX_MAP("ld17", "displaya"),
+ TEGRA_PINMUX_MAP("ldc", "displaya"),
+ TEGRA_PINMUX_MAP("ldi", "displaya"),
+ TEGRA_PINMUX_MAP("lhp0", "displaya"),
+ TEGRA_PINMUX_MAP("lhp1", "displaya"),
+ TEGRA_PINMUX_MAP("lhp2", "displaya"),
+ TEGRA_PINMUX_MAP("lhs", "displaya"),
+ TEGRA_PINMUX_MAP("lm0", "displaya"),
+ TEGRA_PINMUX_MAP("lm1", "displaya"),
+ TEGRA_PINMUX_MAP("lpp", "displaya"),
+ TEGRA_PINMUX_MAP("lpw0", "displaya"),
+ TEGRA_PINMUX_MAP("lpw1", "displaya"),
+ TEGRA_PINMUX_MAP("lpw2", "displaya"),
+ TEGRA_PINMUX_MAP("lsc0", "displaya"),
+ TEGRA_PINMUX_MAP("lsc1", "displaya"),
+ TEGRA_PINMUX_MAP("lsck", "displaya"),
+ TEGRA_PINMUX_MAP("lsda", "displaya"),
+ TEGRA_PINMUX_MAP("lsdi", "displaya"),
+ TEGRA_PINMUX_MAP("lspi", "displaya"),
+ TEGRA_PINMUX_MAP("lvp0", "displaya"),
+ TEGRA_PINMUX_MAP("lvp1", "displaya"),
+ TEGRA_PINMUX_MAP("lvs", "displaya"),
+ TEGRA_PINMUX_MAP("owc", "owr"),
+ TEGRA_PINMUX_MAP("pmc", "pwr_on"),
+ TEGRA_PINMUX_MAP("pta", "hdmi"),
+ TEGRA_PINMUX_MAP("rm", "i2c1"),
+ TEGRA_PINMUX_MAP("sdb", "pwm"),
+ TEGRA_PINMUX_MAP("sdc", "twc"),
+ TEGRA_PINMUX_MAP("sdd", "pwm"),
+ TEGRA_PINMUX_MAP("sdio1", "sdio1"),
+ TEGRA_PINMUX_MAP("slxa", "pcie"),
+ TEGRA_PINMUX_MAP("slxc", "spi4"),
+ TEGRA_PINMUX_MAP("slxd", "spi4"),
+ TEGRA_PINMUX_MAP("slxk", "pcie"),
+ TEGRA_PINMUX_MAP("spdi", "rsvd2"),
+ TEGRA_PINMUX_MAP("spdo", "rsvd2"),
+ TEGRA_PINMUX_MAP("spia", "gmi"),
+ TEGRA_PINMUX_MAP("spib", "gmi"),
+ TEGRA_PINMUX_MAP("spic", "gmi"),
+ TEGRA_PINMUX_MAP("spid", "gmi"),
+ TEGRA_PINMUX_MAP("spie", "gmi"),
+ TEGRA_PINMUX_MAP("spif", "rsvd4"),
+ TEGRA_PINMUX_MAP("spig", "spi2_alt"),
+ TEGRA_PINMUX_MAP("spih", "spi2_alt"),
+ TEGRA_PINMUX_MAP("uaa", "ulpi"),
+ TEGRA_PINMUX_MAP("uab", "ulpi"),
+ TEGRA_PINMUX_MAP("uac", "rsvd4"),
+ TEGRA_PINMUX_MAP("uad", "spdif"),
+ TEGRA_PINMUX_MAP("uca", "uartc"),
+ TEGRA_PINMUX_MAP("ucb", "uartc"),
+ TEGRA_PINMUX_MAP("uda", "ulpi"),
+};
+
+static struct tegra_board_pinmux_pg_conf paz00_pg[] = {
+ {"ata", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"atb", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"atc", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"atd", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"ate", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"cdev1", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"cdev2", TEGRA_PINCONFIG_PULL_DOWN, TEGRA_PINCONFIG_DRIVEN},
+ {"crtp", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"csus", TEGRA_PINCONFIG_PULL_DOWN, TEGRA_PINCONFIG_TRISTATE},
+ {"dap1", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"dap2", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"dap3", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"dap4", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"ddc", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DRIVEN},
+ {"dta", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"dtb", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"dtc", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"dtd", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"dte", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"dtf", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"gma", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"gmb", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"gmc", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"gmd", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"gme", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"gpu", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"gpu7", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"gpv", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"hdint", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"i2cp", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"irrx", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DRIVEN},
+ {"irtx", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DRIVEN},
+ {"kbca", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DRIVEN},
+ {"kbcb", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DRIVEN},
+ {"kbcc", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DRIVEN},
+ {"kbcd", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DRIVEN},
+ {"kbce", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DRIVEN},
+ {"kbcf", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DRIVEN},
+ {"lcsn", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"ld0", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld1", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld2", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld3", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld4", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld5", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld6", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld7", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld8", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld9", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld10", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld11", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld12", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld13", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld14", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld15", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld16", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld17", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ldc", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ldi", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lhp0", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"lhp1", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"lhp2", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"lhs", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lm0", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"lm1", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"lpp", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"lpw0", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"lpw1", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"lpw2", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"lsc0", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lsc1", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"lsck", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"lsda", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"lsdi", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"lspi", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lvp0", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"lvp1", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"lvs", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"owc", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"pmc", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"pta", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"rm", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"sdb", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"sdc", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"sdd", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"sdio1", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"slxa", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"slxc", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"slxd", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"slxk", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"spdi", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"spdo", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"spia", TEGRA_PINCONFIG_PULL_DOWN, TEGRA_PINCONFIG_TRISTATE},
+ {"spib", TEGRA_PINCONFIG_PULL_DOWN, TEGRA_PINCONFIG_TRISTATE},
+ {"spic", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DRIVEN},
+ {"spid", TEGRA_PINCONFIG_PULL_DOWN, TEGRA_PINCONFIG_TRISTATE},
+ {"spie", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"spif", TEGRA_PINCONFIG_PULL_DOWN, TEGRA_PINCONFIG_TRISTATE},
+ {"spig", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DRIVEN},
+ {"spih", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"uaa", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DRIVEN},
+ {"uab", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DRIVEN},
+ {"uac", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"uad", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"uca", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"ucb", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"uda", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"ck32", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"ddrc", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"pmca", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"pmcb", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"pmcc", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"pmcd", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"pmce", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"xm2c", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"xm2d", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"ls", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DONT_SET},
+ {"lc", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DONT_SET},
+ {"ld17_0", TEGRA_PINCONFIG_PULL_DOWN, TEGRA_PINCONFIG_DONT_SET},
+ {"ld19_18", TEGRA_PINCONFIG_PULL_DOWN, TEGRA_PINCONFIG_DONT_SET},
+ {"ld21_20", TEGRA_PINCONFIG_PULL_DOWN, TEGRA_PINCONFIG_DONT_SET},
+ {"ld23_22", TEGRA_PINCONFIG_PULL_DOWN, TEGRA_PINCONFIG_DONT_SET},
};

static struct tegra_gpio_table gpio_table[] = {
@@ -155,8 +267,10 @@ static struct tegra_gpio_table gpio_table[] = {
};

static struct tegra_board_pinmux_conf conf = {
- .pgs = paz00_pinmux,
- .pg_count = ARRAY_SIZE(paz00_pinmux),
+ .maps = paz00_map,
+ .map_count = ARRAY_SIZE(paz00_map),
+ .pgs = paz00_pg,
+ .pg_count = ARRAY_SIZE(paz00_pg),
.gpios = gpio_table,
.gpio_count = ARRAY_SIZE(gpio_table),
};
diff --git a/arch/arm/mach-tegra/board-pinmux.c b/arch/arm/mach-tegra/board-pinmux.c
index adc3efe..4e18e14 100644
--- a/arch/arm/mach-tegra/board-pinmux.c
+++ b/arch/arm/mach-tegra/board-pinmux.c
@@ -16,10 +16,10 @@
#include <linux/kernel.h>
#include <linux/notifier.h>
#include <linux/of.h>
+#include <linux/pinctrl/pinconf.h>
#include <linux/string.h>

#include <mach/gpio-tegra.h>
-#include <mach/pinmux.h>

#include "board-pinmux.h"
#include "devices.h"
@@ -38,19 +38,58 @@ static void tegra_board_pinmux_setup_gpios(void)
}
}

+static inline void tegra_board_pinmux_conf(const char *group, u16 param,
+ u16 arg)
+{
+ if (arg == TEGRA_PINCONFIG_DONT_SET)
+ return;
+ pin_config_group_set(PINMUX_DEV, group, TEGRA_PINCONF_PACK(param, arg));
+}
+
static void tegra_board_pinmux_setup_pinmux(void)
{
- int i;
+ int i, j;
+ const char *group;

for (i = 0; i < ARRAY_SIZE(confs); i++) {
if (!confs[i])
continue;

- tegra_pinmux_config_table(confs[i]->pgs, confs[i]->pg_count);
-
- if (confs[i]->drives)
- tegra_drive_pinmux_config_table(confs[i]->drives,
- confs[i]->drive_count);
+ for (j = 0; j < confs[i]->pg_count; j++) {
+ group = confs[i]->pgs[j].group;
+ tegra_board_pinmux_conf(group,
+ TEGRA_PINCONF_PARAM_PULL,
+ confs[i]->pgs[j].pull);
+ tegra_board_pinmux_conf(group,
+ TEGRA_PINCONF_PARAM_TRISTATE,
+ confs[i]->pgs[j].tristate);
+ }
+
+ for (j = 0; j < confs[i]->drive_count; j++) {
+ group = confs[i]->drives[j].group;
+
+ tegra_board_pinmux_conf(group,
+ TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE,
+ confs[i]->drives[j].high_speed_mode);
+ tegra_board_pinmux_conf(group,
+ TEGRA_PINCONF_PARAM_SCHMITT,
+ confs[i]->drives[j].schmitt);
+ tegra_board_pinmux_conf(group,
+ TEGRA_PINCONF_PARAM_LOW_POWER_MODE,
+ confs[i]->drives[j].low_power_mode);
+ tegra_board_pinmux_conf(group,
+ TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH,
+ confs[i]->drives[j].drive_down_strength);
+ tegra_board_pinmux_conf(group,
+ TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH,
+ confs[i]->drives[j].drive_up_strength);
+ tegra_board_pinmux_conf(group,
+ TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING,
+ confs[i]->drives[j].slew_falling);
+ tegra_board_pinmux_conf(group,
+ TEGRA_PINCONF_PARAM_SLEW_RATE_RISING,
+ confs[i]->drives[j].slew_rising);
+ }
}
}

@@ -94,9 +133,18 @@ static struct platform_device *devices[] = {
void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
struct tegra_board_pinmux_conf *conf_b)
{
+ int i;
+
confs[0] = conf_a;
confs[1] = conf_b;

+ for (i = 0; i < ARRAY_SIZE(confs); i++) {
+ if (!confs[i])
+ continue;
+
+ pinmux_register_mappings(confs[i]->maps, confs[i]->map_count);
+ }
+
bus_register_notifier(&platform_bus_type, &nb);

if (!of_machine_is_compatible("nvidia,tegra20"))
diff --git a/arch/arm/mach-tegra/board-pinmux.h b/arch/arm/mach-tegra/board-pinmux.h
index 4aac735..22c9a6e 100644
--- a/arch/arm/mach-tegra/board-pinmux.h
+++ b/arch/arm/mach-tegra/board-pinmux.h
@@ -15,17 +15,48 @@
#ifndef __MACH_TEGRA_BOARD_PINMUX_H
#define __MACH_TEGRA_BOARD_PINMUX_H

+#include <linux/pinctrl/machine.h>
+
+#include <mach/pinconf-tegra.h>
+
#define GPIO_DEV "tegra-gpio"
#define PINMUX_DEV "tegra-pinmux"

-struct tegra_pingroup_config;
-struct tegra_gpio_table;
+#define TEGRA_PINMUX_MAP(_group_, _function_) { \
+ .name = _group_, \
+ .ctrl_dev_name = PINMUX_DEV, \
+ .group = _group_, \
+ .function = _function_, \
+ .hog_on_boot = true, \
+}
+
+#define TEGRA_PINCONFIG_DONT_SET 0xffff
+
+struct tegra_board_pinmux_pg_conf {
+ const char *group;
+ u16 pull;
+ u16 tristate;
+};
+
+struct tegra_board_pinmux_drive_conf {
+ const char *group;
+ u16 high_speed_mode;
+ u16 schmitt;
+ u16 low_power_mode;
+ u16 drive_down_strength;
+ u16 drive_up_strength;
+ u16 slew_falling;
+ u16 slew_rising;
+};

struct tegra_board_pinmux_conf {
- struct tegra_pingroup_config *pgs;
+ struct pinmux_map *maps;
+ int map_count;
+
+ struct tegra_board_pinmux_pg_conf *pgs;
int pg_count;

- struct tegra_drive_pingroup_config *drives;
+ struct tegra_board_pinmux_drive_conf *drives;
int drive_count;

struct tegra_gpio_table *gpios;
diff --git a/arch/arm/mach-tegra/board-seaboard-pinmux.c b/arch/arm/mach-tegra/board-seaboard-pinmux.c
index 55e7e43..eefc113 100644
--- a/arch/arm/mach-tegra/board-seaboard-pinmux.c
+++ b/arch/arm/mach-tegra/board-seaboard-pinmux.c
@@ -14,169 +14,287 @@
*/

#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <linux/of.h>
-
-#include <mach/pinmux.h>
-#include <mach/pinmux-tegra20.h>

#include "gpio-names.h"
-#include "board-pinmux.h"
#include "board-seaboard.h"
+#include "board-pinmux.h"

-#define DEFAULT_DRIVE(_name) \
- { \
- .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \
- .hsm = TEGRA_HSM_DISABLE, \
- .schmitt = TEGRA_SCHMITT_ENABLE, \
- .drive = TEGRA_DRIVE_DIV_1, \
- .pull_down = TEGRA_PULL_31, \
- .pull_up = TEGRA_PULL_31, \
- .slew_rising = TEGRA_SLEW_SLOWEST, \
- .slew_falling = TEGRA_SLEW_SLOWEST, \
+#define DEFAULT_DRIVE(name) \
+ { \
+ .group = name, \
+ .high_speed_mode = 0, \
+ .schmitt = 0, \
+ .low_power_mode = 3, \
+ .drive_down_strength = 31, \
+ .drive_up_strength = 31, \
+ .slew_falling = 3, \
+ .slew_rising = 3, \
}

-static struct tegra_drive_pingroup_config seaboard_drive_pinmux[] = {
- DEFAULT_DRIVE(SDIO1),
+static struct tegra_board_pinmux_drive_conf seaboard_drive[] = {
+ DEFAULT_DRIVE("drive_sdio1"),
+};
+
+static struct pinmux_map common_map[] = {
+ TEGRA_PINMUX_MAP("ata", "ide"),
+ TEGRA_PINMUX_MAP("atb", "sdio4"),
+ TEGRA_PINMUX_MAP("atc", "nand"),
+ TEGRA_PINMUX_MAP("atd", "gmi"),
+ TEGRA_PINMUX_MAP("ate", "gmi"),
+ TEGRA_PINMUX_MAP("cdev1", "plla_out"),
+ TEGRA_PINMUX_MAP("cdev2", "pllp_out4"),
+ TEGRA_PINMUX_MAP("crtp", "crt"),
+ TEGRA_PINMUX_MAP("csus", "vi_sensor_clk"),
+ TEGRA_PINMUX_MAP("dap1", "dap1"),
+ TEGRA_PINMUX_MAP("dap2", "dap2"),
+ TEGRA_PINMUX_MAP("dap3", "dap3"),
+ TEGRA_PINMUX_MAP("dap4", "dap4"),
+ TEGRA_PINMUX_MAP("ddc", "rsvd2"),
+ TEGRA_PINMUX_MAP("dta", "vi"),
+ TEGRA_PINMUX_MAP("dtb", "vi"),
+ TEGRA_PINMUX_MAP("dtc", "vi"),
+ TEGRA_PINMUX_MAP("dtd", "vi"),
+ TEGRA_PINMUX_MAP("dte", "vi"),
+ TEGRA_PINMUX_MAP("dtf", "i2c3"),
+ TEGRA_PINMUX_MAP("gma", "sdio4"),
+ TEGRA_PINMUX_MAP("gmb", "gmi"),
+ TEGRA_PINMUX_MAP("gmc", "uartd"),
+ TEGRA_PINMUX_MAP("gmd", "sflash"),
+ TEGRA_PINMUX_MAP("gme", "sdio4"),
+ TEGRA_PINMUX_MAP("gpu", "pwm"),
+ TEGRA_PINMUX_MAP("gpu7", "rtck"),
+ TEGRA_PINMUX_MAP("gpv", "pcie"),
+ TEGRA_PINMUX_MAP("hdint", "hdmi"),
+ TEGRA_PINMUX_MAP("i2cp", "i2cp"),
+ TEGRA_PINMUX_MAP("irrx", "uartb"),
+ TEGRA_PINMUX_MAP("irtx", "uartb"),
+ TEGRA_PINMUX_MAP("kbca", "kbc"),
+ TEGRA_PINMUX_MAP("kbcb", "kbc"),
+ TEGRA_PINMUX_MAP("kbcc", "kbc"),
+ TEGRA_PINMUX_MAP("kbcd", "kbc"),
+ TEGRA_PINMUX_MAP("kbce", "kbc"),
+ TEGRA_PINMUX_MAP("kbcf", "kbc"),
+ TEGRA_PINMUX_MAP("lcsn", "rsvd4"),
+ TEGRA_PINMUX_MAP("ld0", "displaya"),
+ TEGRA_PINMUX_MAP("ld1", "displaya"),
+ TEGRA_PINMUX_MAP("ld2", "displaya"),
+ TEGRA_PINMUX_MAP("ld3", "displaya"),
+ TEGRA_PINMUX_MAP("ld4", "displaya"),
+ TEGRA_PINMUX_MAP("ld5", "displaya"),
+ TEGRA_PINMUX_MAP("ld6", "displaya"),
+ TEGRA_PINMUX_MAP("ld7", "displaya"),
+ TEGRA_PINMUX_MAP("ld8", "displaya"),
+ TEGRA_PINMUX_MAP("ld9", "displaya"),
+ TEGRA_PINMUX_MAP("ld10", "displaya"),
+ TEGRA_PINMUX_MAP("ld11", "displaya"),
+ TEGRA_PINMUX_MAP("ld12", "displaya"),
+ TEGRA_PINMUX_MAP("ld13", "displaya"),
+ TEGRA_PINMUX_MAP("ld14", "displaya"),
+ TEGRA_PINMUX_MAP("ld15", "displaya"),
+ TEGRA_PINMUX_MAP("ld16", "displaya"),
+ TEGRA_PINMUX_MAP("ld17", "displaya"),
+ TEGRA_PINMUX_MAP("ldc", "rsvd4"),
+ TEGRA_PINMUX_MAP("ldi", "displaya"),
+ TEGRA_PINMUX_MAP("lhp0", "displaya"),
+ TEGRA_PINMUX_MAP("lhp1", "displaya"),
+ TEGRA_PINMUX_MAP("lhp2", "displaya"),
+ TEGRA_PINMUX_MAP("lhs", "displaya"),
+ TEGRA_PINMUX_MAP("lm0", "rsvd4"),
+ TEGRA_PINMUX_MAP("lm1", "crt"),
+ TEGRA_PINMUX_MAP("lpp", "displaya"),
+ TEGRA_PINMUX_MAP("lpw1", "rsvd4"),
+ TEGRA_PINMUX_MAP("lsc0", "displaya"),
+ TEGRA_PINMUX_MAP("lsdi", "rsvd4"),
+ TEGRA_PINMUX_MAP("lspi", "displaya"),
+ TEGRA_PINMUX_MAP("lvp0", "rsvd4"),
+ TEGRA_PINMUX_MAP("lvp1", "displaya"),
+ TEGRA_PINMUX_MAP("lvs", "displaya"),
+ TEGRA_PINMUX_MAP("owc", "rsvd2"),
+ TEGRA_PINMUX_MAP("pmc", "pwr_on"),
+ TEGRA_PINMUX_MAP("pta", "hdmi"),
+ TEGRA_PINMUX_MAP("rm", "i2c1"),
+ TEGRA_PINMUX_MAP("sdb", "sdio3"),
+ TEGRA_PINMUX_MAP("sdc", "sdio3"),
+ TEGRA_PINMUX_MAP("sdd", "sdio3"),
+ TEGRA_PINMUX_MAP("sdio1", "sdio1"),
+ TEGRA_PINMUX_MAP("slxa", "pcie"),
+ TEGRA_PINMUX_MAP("slxd", "spdif"),
+ TEGRA_PINMUX_MAP("spdi", "rsvd2"),
+ TEGRA_PINMUX_MAP("spdo", "rsvd2"),
+ TEGRA_PINMUX_MAP("spia", "gmi"),
+ TEGRA_PINMUX_MAP("spib", "gmi"),
+ TEGRA_PINMUX_MAP("spic", "gmi"),
+ TEGRA_PINMUX_MAP("spid", "spi1"),
+ TEGRA_PINMUX_MAP("spie", "spi1"),
+ TEGRA_PINMUX_MAP("spif", "spi1"),
+ TEGRA_PINMUX_MAP("spig", "spi2_alt"),
+ TEGRA_PINMUX_MAP("spih", "spi2_alt"),
+ TEGRA_PINMUX_MAP("uaa", "ulpi"),
+ TEGRA_PINMUX_MAP("uab", "ulpi"),
+ TEGRA_PINMUX_MAP("uac", "rsvd2"),
+ TEGRA_PINMUX_MAP("uad", "irda"),
+ TEGRA_PINMUX_MAP("uca", "uartc"),
+ TEGRA_PINMUX_MAP("ucb", "uartc"),
+ TEGRA_PINMUX_MAP("uda", "ulpi"),
+};
+
+static struct pinmux_map seaboard_map[] = {
+ TEGRA_PINMUX_MAP("lpw0", "hdmi"),
+ TEGRA_PINMUX_MAP("lpw2", "hdmi"),
+ TEGRA_PINMUX_MAP("lsc1", "hdmi"),
+ TEGRA_PINMUX_MAP("lsck", "hdmi"),
+ TEGRA_PINMUX_MAP("lsda", "hdmi"),
+ TEGRA_PINMUX_MAP("slxc", "spdif"),
+ TEGRA_PINMUX_MAP("slxk", "pcie"),
+};
+
+static struct pinmux_map ventana_map[] = {
+ TEGRA_PINMUX_MAP("lpw0", "displaya"),
+ TEGRA_PINMUX_MAP("lpw2", "displaya"),
+ TEGRA_PINMUX_MAP("lsc1", "displaya"),
+ TEGRA_PINMUX_MAP("lsck", "displaya"),
+ TEGRA_PINMUX_MAP("lsda", "displaya"),
+ TEGRA_PINMUX_MAP("slxc", "sdio3"),
+ TEGRA_PINMUX_MAP("slxk", "sdio3"),
};

-static struct tegra_pingroup_config common_pinmux[] = {
- {TEGRA_PINGROUP_ATA, TEGRA_MUX_IDE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_DTA, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_DTB, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_DTC, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_DTD, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_DTE, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_GMB, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_GMC, TEGRA_MUX_UARTD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_GME, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_GPU, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTB, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTB, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_KBCB, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_KBCD, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LCSN, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LDC, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LM0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LM1, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LPW1, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LSDI, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LVP0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_OWC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_SDB, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_SDC, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_SDD, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_SPDI, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_UAD, TEGRA_MUX_IRDA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+static struct tegra_board_pinmux_pg_conf common_pg[] = {
+ {"ata", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"atb", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"atc", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"atd", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"ate", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"cdev1", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"cdev2", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"crtp", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"csus", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"dap1", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"dap2", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"dap3", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"dap4", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"dta", TEGRA_PINCONFIG_PULL_DOWN, TEGRA_PINCONFIG_DRIVEN},
+ {"dtb", TEGRA_PINCONFIG_PULL_DOWN, TEGRA_PINCONFIG_DRIVEN},
+ {"dtc", TEGRA_PINCONFIG_PULL_DOWN, TEGRA_PINCONFIG_DRIVEN},
+ {"dtd", TEGRA_PINCONFIG_PULL_DOWN, TEGRA_PINCONFIG_DRIVEN},
+ {"dte", TEGRA_PINCONFIG_PULL_DOWN, TEGRA_PINCONFIG_TRISTATE},
+ {"dtf", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"gma", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"gmb", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"gmc", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"gme", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"gpu", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"gpu7", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"gpv", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"hdint", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"i2cp", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"irrx", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"irtx", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"kbca", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DRIVEN},
+ {"kbcb", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DRIVEN},
+ {"kbcc", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DRIVEN},
+ {"kbcd", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DRIVEN},
+ {"kbce", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DRIVEN},
+ {"kbcf", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DRIVEN},
+ {"lcsn", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"ld0", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld1", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld2", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld3", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld4", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld5", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld6", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld7", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld8", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld9", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld10", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld11", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld12", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld13", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld14", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld15", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld16", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld17", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ldc", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"ldi", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lhp0", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lhp1", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lhp2", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lhs", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lm0", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lm1", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"lpp", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lpw0", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lpw1", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"lpw2", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lsc0", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lsck", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"lsda", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"lsdi", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"lspi", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lvp0", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"lvp1", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lvs", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"owc", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"pmc", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"rm", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"sdb", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"sdc", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"sdd", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"sdio1", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DRIVEN},
+ {"slxa", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"slxd", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"slxk", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"spdi", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"spdo", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"spib", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"spid", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"spie", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"spif", TEGRA_PINCONFIG_PULL_DOWN, TEGRA_PINCONFIG_TRISTATE},
+ {"spih", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"uaa", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DRIVEN},
+ {"uab", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DRIVEN},
+ {"uac", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"uad", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"uca", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"ucb", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"uda", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"ck32", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"ddrc", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"pmca", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"pmcb", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"pmcc", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"pmcd", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"pmce", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"xm2c", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"xm2d", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"ls", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"lc", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"ld17_0", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"ld19_18", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"ld21_20", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"ld23_22", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
};

-static struct tegra_pingroup_config seaboard_pinmux[] = {
- {TEGRA_PINGROUP_DDC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_GMD, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LPW0, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LPW2, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LSC1, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LSCK, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LSDA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_PTA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
+static struct tegra_board_pinmux_pg_conf seaboard_pg[] = {
+ {"ddc", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"gmd", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"lsc1", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"pta", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"slxc", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"spia", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"spic", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DRIVEN},
+ {"spig", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
};

-static struct tegra_pingroup_config ventana_pinmux[] = {
- {TEGRA_PINGROUP_DDC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_GMD, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LPW0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LPW2, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LSC1, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LSCK, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LSDA, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_PTA, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_SLXK, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+static struct tegra_board_pinmux_pg_conf ventana_pg[] = {
+ {"ddc", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"gmd", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"lsc1", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"pta", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"slxc", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"spia", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"spic", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"spig", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
};

static struct tegra_gpio_table common_gpio_table[] = {
@@ -204,24 +322,30 @@ static struct tegra_gpio_table ventana_gpio_table[] = {
};

static struct tegra_board_pinmux_conf common_conf = {
- .pgs = common_pinmux,
- .pg_count = ARRAY_SIZE(common_pinmux),
+ .maps = common_map,
+ .map_count = ARRAY_SIZE(common_map),
+ .pgs = common_pg,
+ .pg_count = ARRAY_SIZE(common_pg),
.gpios = common_gpio_table,
.gpio_count = ARRAY_SIZE(common_gpio_table),
};

static struct tegra_board_pinmux_conf seaboard_conf = {
- .pgs = seaboard_pinmux,
- .pg_count = ARRAY_SIZE(seaboard_pinmux),
- .drives = seaboard_drive_pinmux,
- .drive_count = ARRAY_SIZE(seaboard_drive_pinmux),
+ .maps = seaboard_map,
+ .map_count = ARRAY_SIZE(seaboard_map),
+ .pgs = seaboard_pg,
+ .pg_count = ARRAY_SIZE(seaboard_pg),
+ .drives = seaboard_drive,
+ .drive_count = ARRAY_SIZE(seaboard_drive),
.gpios = seaboard_gpio_table,
.gpio_count = ARRAY_SIZE(seaboard_gpio_table),
};

static struct tegra_board_pinmux_conf ventana_conf = {
- .pgs = ventana_pinmux,
- .pg_count = ARRAY_SIZE(ventana_pinmux),
+ .maps = ventana_map,
+ .map_count = ARRAY_SIZE(ventana_map),
+ .pgs = ventana_pg,
+ .pg_count = ARRAY_SIZE(ventana_pg),
.gpios = ventana_gpio_table,
.gpio_count = ARRAY_SIZE(ventana_gpio_table),
};
diff --git a/arch/arm/mach-tegra/board-trimslice-pinmux.c b/arch/arm/mach-tegra/board-trimslice-pinmux.c
index a21a2be..7a73bbe 100644
--- a/arch/arm/mach-tegra/board-trimslice-pinmux.c
+++ b/arch/arm/mach-tegra/board-trimslice-pinmux.c
@@ -2,6 +2,7 @@
* arch/arm/mach-tegra/board-trimslice-pinmux.c
*
* Copyright (C) 2011 CompuLab, Ltd.
+ * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -13,135 +14,246 @@
* GNU General Public License for more details.
*
*/
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/of.h>

-#include <mach/pinmux.h>
-#include <mach/pinmux-tegra20.h>
+#include <linux/kernel.h>

#include "gpio-names.h"
-#include "board-pinmux.h"
#include "board-trimslice.h"
+#include "board-pinmux.h"
+
+static struct pinmux_map trimslice_map[] = {
+ TEGRA_PINMUX_MAP("ata", "ide"),
+ TEGRA_PINMUX_MAP("atb", "sdio4"),
+ TEGRA_PINMUX_MAP("atc", "nand"),
+ TEGRA_PINMUX_MAP("atd", "gmi"),
+ TEGRA_PINMUX_MAP("ate", "gmi"),
+ TEGRA_PINMUX_MAP("cdev1", "plla_out"),
+ TEGRA_PINMUX_MAP("cdev2", "pllp_out4"),
+ TEGRA_PINMUX_MAP("crtp", "crt"),
+ TEGRA_PINMUX_MAP("csus", "vi_sensor_clk"),
+ TEGRA_PINMUX_MAP("dap1", "dap1"),
+ TEGRA_PINMUX_MAP("dap2", "dap2"),
+ TEGRA_PINMUX_MAP("dap3", "dap3"),
+ TEGRA_PINMUX_MAP("dap4", "dap4"),
+ TEGRA_PINMUX_MAP("ddc", "i2c2"),
+ TEGRA_PINMUX_MAP("dta", "vi"),
+ TEGRA_PINMUX_MAP("dtb", "vi"),
+ TEGRA_PINMUX_MAP("dtc", "vi"),
+ TEGRA_PINMUX_MAP("dtd", "vi"),
+ TEGRA_PINMUX_MAP("dte", "vi"),
+ TEGRA_PINMUX_MAP("dtf", "i2c3"),
+ TEGRA_PINMUX_MAP("gma", "sdio4"),
+ TEGRA_PINMUX_MAP("gmb", "nand"),
+ TEGRA_PINMUX_MAP("gmc", "sflash"),
+ TEGRA_PINMUX_MAP("gmd", "sflash"),
+ TEGRA_PINMUX_MAP("gme", "gmi"),
+ TEGRA_PINMUX_MAP("gpu", "uarta"),
+ TEGRA_PINMUX_MAP("gpu7", "rtck"),
+ TEGRA_PINMUX_MAP("gpv", "pcie"),
+ TEGRA_PINMUX_MAP("hdint", "hdmi"),
+ TEGRA_PINMUX_MAP("i2cp", "i2cp"),
+ TEGRA_PINMUX_MAP("irrx", "uartb"),
+ TEGRA_PINMUX_MAP("irtx", "uartb"),
+ TEGRA_PINMUX_MAP("kbca", "kbc"),
+ TEGRA_PINMUX_MAP("kbcb", "kbc"),
+ TEGRA_PINMUX_MAP("kbcc", "kbc"),
+ TEGRA_PINMUX_MAP("kbcd", "kbc"),
+ TEGRA_PINMUX_MAP("kbce", "kbc"),
+ TEGRA_PINMUX_MAP("kbcf", "kbc"),
+ TEGRA_PINMUX_MAP("lcsn", "displaya"),
+ TEGRA_PINMUX_MAP("ld0", "displaya"),
+ TEGRA_PINMUX_MAP("ld1", "displaya"),
+ TEGRA_PINMUX_MAP("ld2", "displaya"),
+ TEGRA_PINMUX_MAP("ld3", "displaya"),
+ TEGRA_PINMUX_MAP("ld4", "displaya"),
+ TEGRA_PINMUX_MAP("ld5", "displaya"),
+ TEGRA_PINMUX_MAP("ld6", "displaya"),
+ TEGRA_PINMUX_MAP("ld7", "displaya"),
+ TEGRA_PINMUX_MAP("ld8", "displaya"),
+ TEGRA_PINMUX_MAP("ld9", "displaya"),
+ TEGRA_PINMUX_MAP("ld10", "displaya"),
+ TEGRA_PINMUX_MAP("ld11", "displaya"),
+ TEGRA_PINMUX_MAP("ld12", "displaya"),
+ TEGRA_PINMUX_MAP("ld13", "displaya"),
+ TEGRA_PINMUX_MAP("ld14", "displaya"),
+ TEGRA_PINMUX_MAP("ld15", "displaya"),
+ TEGRA_PINMUX_MAP("ld16", "displaya"),
+ TEGRA_PINMUX_MAP("ld17", "displaya"),
+ TEGRA_PINMUX_MAP("ldc", "displaya"),
+ TEGRA_PINMUX_MAP("ldi", "displaya"),
+ TEGRA_PINMUX_MAP("lhp0", "displaya"),
+ TEGRA_PINMUX_MAP("lhp1", "displaya"),
+ TEGRA_PINMUX_MAP("lhp2", "displaya"),
+ TEGRA_PINMUX_MAP("lhs", "displaya"),
+ TEGRA_PINMUX_MAP("lm0", "displaya"),
+ TEGRA_PINMUX_MAP("lm1", "displaya"),
+ TEGRA_PINMUX_MAP("lpp", "displaya"),
+ TEGRA_PINMUX_MAP("lpw0", "displaya"),
+ TEGRA_PINMUX_MAP("lpw1", "displaya"),
+ TEGRA_PINMUX_MAP("lpw2", "displaya"),
+ TEGRA_PINMUX_MAP("lsc0", "displaya"),
+ TEGRA_PINMUX_MAP("lsc1", "displaya"),
+ TEGRA_PINMUX_MAP("lsck", "displaya"),
+ TEGRA_PINMUX_MAP("lsda", "displaya"),
+ TEGRA_PINMUX_MAP("lsdi", "displaya"),
+ TEGRA_PINMUX_MAP("lspi", "displaya"),
+ TEGRA_PINMUX_MAP("lvp0", "displaya"),
+ TEGRA_PINMUX_MAP("lvp1", "displaya"),
+ TEGRA_PINMUX_MAP("lvs", "displaya"),
+ TEGRA_PINMUX_MAP("owc", "rsvd2"),
+ TEGRA_PINMUX_MAP("pmc", "pwr_on"),
+ TEGRA_PINMUX_MAP("pta", "gmi"),
+ TEGRA_PINMUX_MAP("rm", "i2c1"),
+ TEGRA_PINMUX_MAP("sdb", "pwm"),
+ TEGRA_PINMUX_MAP("sdc", "pwm"),
+ TEGRA_PINMUX_MAP("sdd", "pwm"),
+ TEGRA_PINMUX_MAP("sdio1", "sdio1"),
+ TEGRA_PINMUX_MAP("slxa", "pcie"),
+ TEGRA_PINMUX_MAP("slxc", "sdio3"),
+ TEGRA_PINMUX_MAP("slxd", "sdio3"),
+ TEGRA_PINMUX_MAP("slxk", "pcie"),
+ TEGRA_PINMUX_MAP("spdi", "spdif"),
+ TEGRA_PINMUX_MAP("spdo", "spdif"),
+ TEGRA_PINMUX_MAP("spia", "spi2"),
+ TEGRA_PINMUX_MAP("spib", "spi2"),
+ TEGRA_PINMUX_MAP("spic", "spi2"),
+ TEGRA_PINMUX_MAP("spid", "spi1"),
+ TEGRA_PINMUX_MAP("spie", "spi1"),
+ TEGRA_PINMUX_MAP("spif", "spi1"),
+ TEGRA_PINMUX_MAP("spig", "spi2_alt"),
+ TEGRA_PINMUX_MAP("spih", "spi2_alt"),
+ TEGRA_PINMUX_MAP("uaa", "ulpi"),
+ TEGRA_PINMUX_MAP("uab", "ulpi"),
+ TEGRA_PINMUX_MAP("uac", "rsvd2"),
+ TEGRA_PINMUX_MAP("uad", "irda"),
+ TEGRA_PINMUX_MAP("uca", "uartc"),
+ TEGRA_PINMUX_MAP("ucb", "uartc"),
+ TEGRA_PINMUX_MAP("uda", "ulpi"),
+};

-static struct tegra_pingroup_config trimslice_pinmux[] = {
- {TEGRA_PINGROUP_ATA, TEGRA_MUX_IDE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_DDC, TEGRA_MUX_I2C2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_DTA, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_DTB, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_DTC, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_DTD, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_DTE, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_GMB, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_GMC, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_GMD, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_GME, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_GPU, TEGRA_MUX_UARTA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_KBCB, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_KBCD, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LCSN, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LDC, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LM0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LM1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LPW0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LPW1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LPW2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LSC1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LSCK, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LSDA, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LSDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LVP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_OWC, TEGRA_MUX_RSVD2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_PTA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_SDB, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_SDC, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_SDD, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_SPDI, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SPDO, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SPIA, TEGRA_MUX_SPI2, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SPIB, TEGRA_MUX_SPI2, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SPIC, TEGRA_MUX_SPI2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_UAD, TEGRA_MUX_IRDA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+static struct tegra_board_pinmux_pg_conf trimslice_pg[] = {
+ {"ata", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"atb", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"atc", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"atd", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"ate", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"cdev1", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"cdev2", TEGRA_PINCONFIG_PULL_DOWN, TEGRA_PINCONFIG_TRISTATE},
+ {"crtp", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"csus", TEGRA_PINCONFIG_PULL_DOWN, TEGRA_PINCONFIG_TRISTATE},
+ {"dap1", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"dap2", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"dap3", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"dap4", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"ddc", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DRIVEN},
+ {"dta", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"dtb", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"dtc", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"dtd", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"dte", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"dtf", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DRIVEN},
+ {"gma", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"gmb", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"gmc", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"gmd", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"gme", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"gpu", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"gpu7", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"gpv", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"hdint", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"i2cp", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"irrx", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"irtx", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"kbca", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"kbcb", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"kbcc", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"kbcd", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"kbce", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"kbcf", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"lcsn", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"ld0", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld1", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld2", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld3", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld4", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld5", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld6", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld7", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld8", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld9", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld10", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld11", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld12", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld13", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld14", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld15", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld16", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ld17", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"ldc", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"ldi", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lhp0", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lhp1", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lhp2", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lhs", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lm0", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lm1", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"lpp", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lpw0", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lpw1", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"lpw2", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lsc0", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lsc1", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"lsck", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"lsda", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"lsdi", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"lspi", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lvp0", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"lvp1", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"lvs", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"owc", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"pmc", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_TRISTATE},
+ {"pta", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"rm", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DRIVEN},
+ {"sdb", TEGRA_PINCONFIG_DONT_SET, TEGRA_PINCONFIG_DRIVEN},
+ {"sdc", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DRIVEN},
+ {"sdd", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DRIVEN},
+ {"sdio1", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"slxa", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"slxc", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"slxd", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"slxk", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"spdi", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"spdo", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"spia", TEGRA_PINCONFIG_PULL_DOWN, TEGRA_PINCONFIG_TRISTATE},
+ {"spib", TEGRA_PINCONFIG_PULL_DOWN, TEGRA_PINCONFIG_TRISTATE},
+ {"spic", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"spid", TEGRA_PINCONFIG_PULL_DOWN, TEGRA_PINCONFIG_TRISTATE},
+ {"spie", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"spif", TEGRA_PINCONFIG_PULL_DOWN, TEGRA_PINCONFIG_TRISTATE},
+ {"spig", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"spih", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"uaa", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"uab", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"uac", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DRIVEN},
+ {"uad", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"uca", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"ucb", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_TRISTATE},
+ {"uda", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_TRISTATE},
+ {"ck32", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"ddrc", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"pmca", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"pmcb", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"pmcc", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"pmcd", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"pmce", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"xm2c", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"xm2d", TEGRA_PINCONFIG_PULL_NONE, TEGRA_PINCONFIG_DONT_SET},
+ {"ls", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DONT_SET},
+ {"lc", TEGRA_PINCONFIG_PULL_UP, TEGRA_PINCONFIG_DONT_SET},
+ {"ld17_0", TEGRA_PINCONFIG_PULL_DOWN, TEGRA_PINCONFIG_DONT_SET},
+ {"ld19_18", TEGRA_PINCONFIG_PULL_DOWN, TEGRA_PINCONFIG_DONT_SET},
+ {"ld21_20", TEGRA_PINCONFIG_PULL_DOWN, TEGRA_PINCONFIG_DONT_SET},
+ {"ld23_22", TEGRA_PINCONFIG_PULL_DOWN, TEGRA_PINCONFIG_DONT_SET},
};

static struct tegra_gpio_table gpio_table[] = {
@@ -153,8 +265,10 @@ static struct tegra_gpio_table gpio_table[] = {
};

static struct tegra_board_pinmux_conf conf = {
- .pgs = trimslice_pinmux,
- .pg_count = ARRAY_SIZE(trimslice_pinmux),
+ .maps = trimslice_map,
+ .map_count = ARRAY_SIZE(trimslice_map),
+ .pgs = trimslice_pg,
+ .pg_count = ARRAY_SIZE(trimslice_pg),
.gpios = gpio_table,
.gpio_count = ARRAY_SIZE(gpio_table),
};
diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c
index ac35d2b..7867a12 100644
--- a/arch/arm/mach-tegra/pinmux.c
+++ b/arch/arm/mach-tegra/pinmux.c
@@ -711,10 +711,10 @@ void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *co

static struct of_device_id tegra_pinmux_of_match[] __devinitdata = {
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
- { .compatible = "nvidia,tegra20-pinmux", tegra20_pinmux_init },
+ { .compatible = "nvidia,tegra20-pinmux-disabled", tegra20_pinmux_init },
#endif
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
- { .compatible = "nvidia,tegra30-pinmux", tegra30_pinmux_init },
+ { .compatible = "nvidia,tegra30-pinmux-disabled", tegra30_pinmux_init },
#endif
{ },
};
@@ -809,7 +809,7 @@ static int __devinit tegra_pinmux_probe(struct platform_device *pdev)

static struct platform_driver tegra_pinmux_driver = {
.driver = {
- .name = "tegra-pinmux",
+ .name = "tegra-pinmux-disabled",
.owner = THIS_MODULE,
.of_match_table = tegra_pinmux_of_match,
},
diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c
index 9b32968..7fc8e83 100644
--- a/drivers/pinctrl/pinctrl-tegra.c
+++ b/drivers/pinctrl/pinctrl-tegra.c
@@ -31,7 +31,7 @@

#include "pinctrl-tegra.h"

-#define DRIVER_NAME "tegra-pinmux-disabled"
+#define DRIVER_NAME "tegra-pinmux"

struct tegra_pmx {
struct device *dev;
@@ -422,13 +422,13 @@ static struct pinctrl_desc tegra_pinctrl_desc = {
static struct of_device_id tegra_pinctrl_of_match[] __devinitdata = {
#ifdef CONFIG_PINCTRL_TEGRA20
{
- .compatible = "nvidia,tegra20-pinmux-disabled",
+ .compatible = "nvidia,tegra20-pinmux",
.data = tegra20_pinctrl_init,
},
#endif
#ifdef CONFIG_PINCTRL_TEGRA30
{
- .compatible = "nvidia,tegra30-pinmux-disabled",
+ .compatible = "nvidia,tegra30-pinmux",
.data = tegra30_pinctrl_init,
},
#endif
--
1.7.0.4


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