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    Subject[22/48] radeon: Fix disabling PCI bus mastering on big endian hosts.
    3.1-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Michel Dänzer <michel.daenzer@amd.com>

    commit 3df96909b75835d487a9178761622b0cbd7310d4 upstream.

    It would previously write basically random bits to PCI configuration space...
    Not very surprising that the GPU tended to stop responding completely. The
    resulting MCE even froze the whole machine sometimes.

    Now resetting the GPU after a lockup has at least a fighting chance of
    succeeding.

    Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
    Signed-off-by: Dave Airlie <airlied@redhat.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

    ---
    drivers/gpu/drm/radeon/r100.c | 5 +++--
    drivers/gpu/drm/radeon/rs600.c | 4 ++--
    2 files changed, 5 insertions(+), 4 deletions(-)

    --- a/drivers/gpu/drm/radeon/r100.c
    +++ b/drivers/gpu/drm/radeon/r100.c
    @@ -2069,6 +2069,7 @@ bool r100_gpu_is_lockup(struct radeon_de
    void r100_bm_disable(struct radeon_device *rdev)
    {
    u32 tmp;
    + u16 tmp16;

    /* disable bus mastering */
    tmp = RREG32(R_000030_BUS_CNTL);
    @@ -2079,8 +2080,8 @@ void r100_bm_disable(struct radeon_devic
    WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
    tmp = RREG32(RADEON_BUS_CNTL);
    mdelay(1);
    - pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);
    - pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
    + pci_read_config_word(rdev->pdev, 0x4, &tmp16);
    + pci_write_config_word(rdev->pdev, 0x4, tmp16 & 0xFFFB);
    mdelay(1);
    }

    --- a/drivers/gpu/drm/radeon/rs600.c
    +++ b/drivers/gpu/drm/radeon/rs600.c
    @@ -324,10 +324,10 @@ void rs600_hpd_fini(struct radeon_device

    void rs600_bm_disable(struct radeon_device *rdev)
    {
    - u32 tmp;
    + u16 tmp;

    /* disable bus mastering */
    - pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);
    + pci_read_config_word(rdev->pdev, 0x4, &tmp);
    pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
    mdelay(1);
    }

    --
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