lkml.org 
[lkml]   [2011]   [Sep]   [29]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH 20/21] drm/i915: Restrict ILK-specific eDP power hack to ILK
    Date
    This eliminates a fairly long delay when power sequencing newer
    hardware

    Signed-off-by: Keith Packard <keithp@keithp.com>
    ---
    drivers/gpu/drm/i915/intel_dp.c | 51 +++++++++++++++++++++++----------------
    1 files changed, 30 insertions(+), 21 deletions(-)

    diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
    index 7120ba7..f223504 100644
    --- a/drivers/gpu/drm/i915/intel_dp.c
    +++ b/drivers/gpu/drm/i915/intel_dp.c
    @@ -986,10 +986,12 @@ static void ironlake_edp_panel_on (struct intel_dp *intel_dp)
    pp &= ~PANEL_UNLOCK_MASK;
    pp |= PANEL_UNLOCK_REGS;

    - /* ILK workaround: disable reset around power sequence */
    - pp &= ~PANEL_POWER_RESET;
    - I915_WRITE(PCH_PP_CONTROL, pp);
    - POSTING_READ(PCH_PP_CONTROL);
    + if (IS_GEN5(dev)) {
    + /* ILK workaround: disable reset around power sequence */
    + pp &= ~PANEL_POWER_RESET;
    + I915_WRITE(PCH_PP_CONTROL, pp);
    + POSTING_READ(PCH_PP_CONTROL);
    + }

    pp |= POWER_TARGET_ON;
    I915_WRITE(PCH_PP_CONTROL, pp);
    @@ -1000,9 +1002,11 @@ static void ironlake_edp_panel_on (struct intel_dp *intel_dp)
    DRM_ERROR("panel on wait timed out: 0x%08x\n",
    I915_READ(PCH_PP_STATUS));

    - pp |= PANEL_POWER_RESET; /* restore panel reset bit */
    - I915_WRITE(PCH_PP_CONTROL, pp);
    - POSTING_READ(PCH_PP_CONTROL);
    + if (IS_GEN5(dev)) {
    + pp |= PANEL_POWER_RESET; /* restore panel reset bit */
    + I915_WRITE(PCH_PP_CONTROL, pp);
    + POSTING_READ(PCH_PP_CONTROL);
    + }
    }

    static void ironlake_edp_panel_off_sync(struct intel_dp *intel_dp)
    @@ -1019,23 +1023,28 @@ static void ironlake_edp_panel_off_sync(struct intel_dp *intel_dp)
    pp &= ~PANEL_UNLOCK_MASK;
    pp |= PANEL_UNLOCK_REGS;

    - /* ILK workaround: disable reset around power sequence */
    - pp &= ~PANEL_POWER_RESET;
    - I915_WRITE(PCH_PP_CONTROL, pp);
    - POSTING_READ(PCH_PP_CONTROL);
    + if (IS_GEN5(dev)) {
    + /* ILK workaround: disable reset around power sequence */
    + pp &= ~PANEL_POWER_RESET;
    + I915_WRITE(PCH_PP_CONTROL, pp);
    + POSTING_READ(PCH_PP_CONTROL);
    + }

    - pp &= ~POWER_TARGET_ON;
    - I915_WRITE(PCH_PP_CONTROL, pp);
    - POSTING_READ(PCH_PP_CONTROL);
    + intel_dp->panel_off_jiffies = jiffies;

    - if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
    - DRM_ERROR("panel off wait timed out: 0x%08x\n",
    - I915_READ(PCH_PP_STATUS));
    + if (IS_GEN5(dev)) {
    + pp &= ~POWER_TARGET_ON;
    + I915_WRITE(PCH_PP_CONTROL, pp);
    + POSTING_READ(PCH_PP_CONTROL);

    - pp |= PANEL_POWER_RESET; /* restore panel reset bit */
    - I915_WRITE(PCH_PP_CONTROL, pp);
    - POSTING_READ(PCH_PP_CONTROL);
    - intel_dp->panel_off_jiffies = jiffies;
    + if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
    + DRM_ERROR("panel off wait timed out: 0x%08x\n",
    + I915_READ(PCH_PP_STATUS));
    +
    + pp |= PANEL_POWER_RESET; /* restore panel reset bit */
    + I915_WRITE(PCH_PP_CONTROL, pp);
    + POSTING_READ(PCH_PP_CONTROL);
    + }
    }

    static void ironlake_edp_panel_off(struct drm_encoder *encoder, bool sync)
    --
    1.7.6.3


    \
     
     \ /
      Last update: 2011-09-30 03:13    [W:0.030 / U:35.316 seconds]
    ©2003-2016 Jasper Spaans. hosted at Digital OceanAdvertise on this site