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    SubjectRe: [PATCH v3 00/24] C6X: New architecture
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    On Thu, 2011-09-29 at 12:33 +0200, Arnd Bergmann wrote:
    > On Wednesday 28 September 2011, Valdis.Kletnieks@vt.edu wrote:
    > > Show Details
    > > On Tue, 27 Sep 2011 16:29:41 EDT, Mark Salter said:
    > >
    > > > This architecture supports members of the Texas Instruments family
    > > > of C6x single and multicore DSPs. The multicore DSPs do not support
    > > > cache coherancy, so are not suitable for SMP.
    > >
    > > Is there a usage model for the multicore? I know somebody had some patches for
    > > "HPC dedicated compute cores" that would just basically run a userspace process
    > > and that's it - would those be applicable here?
    >
    > No, that's a different thing. Even with dedicated compute cores, you need
    > cache coherency.

    One thing that we plan to push later is an XIP model where cores can
    share a
    single kernel text image but run with their own copies of data. So you
    end up
    with something like a loosely coupled multiprocessor system with some
    hardware
    support for multicore communication and peripheral sharing.

    --Mark




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