[lkml]   [2011]   [Sep]   [23]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
SubjectRe: [V3][PATCH 0/7] perf, x86: Implement AMD IBS
On 23.09.11 07:48:43, Peter Zijlstra wrote:

> There was also the thing about putting perf_event_set_period() and
> perf_event_try_update() in a common library and converting all pmu
> implementations to use them.
> As well as the for_each_set_bit_continue() thing which you've got
> queued.

Yeah, I will post separate patches for this.

> Anyway, I read through the stuff and it looks about right, so I'll wait
> for Don to post his NMI infrastructure bits once more (he had some
> pending changes) and then I'll queue this on top.

Many thanks.

> The only thing I'm not quite sure on is the userspace bits, but those
> are in the future work section as well, but possibly Ingo has a strong
> opinion here, sadly he doesn't have email atm :/

With Lin's patch 'perf: Remove perf_event_attr::type check' we already
can sample with perf record.

I think we could extend perf report to parse also ibs samples. The
only thing we need for it should be the pmu name/type mapping in the header and the pmu type in the sample. See my comment on
Stephane's patch '[PATCH] perf: make more self-descriptive



Advanced Micro Devices, Inc.
Operating System Research Center

 \ /
  Last update: 2011-09-23 14:27    [W:0.102 / U:15.528 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site