Messages in this thread | | | Date | Fri, 23 Sep 2011 14:20:14 +0200 | From | Robert Richter <> | Subject | Re: [V3][PATCH 0/7] perf, x86: Implement AMD IBS |
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On 23.09.11 07:48:43, Peter Zijlstra wrote:
> There was also the thing about putting perf_event_set_period() and > perf_event_try_update() in a common library and converting all pmu > implementations to use them. > > As well as the for_each_set_bit_continue() thing which you've got > queued.
Yeah, I will post separate patches for this.
> Anyway, I read through the stuff and it looks about right, so I'll wait > for Don to post his NMI infrastructure bits once more (he had some > pending changes) and then I'll queue this on top.
Many thanks.
> The only thing I'm not quite sure on is the userspace bits, but those > are in the future work section as well, but possibly Ingo has a strong > opinion here, sadly he doesn't have email atm :/
With Lin's patch 'perf: Remove perf_event_attr::type check' we already can sample with perf record.
I think we could extend perf report to parse also ibs samples. The only thing we need for it should be the pmu name/type mapping in the perf.data header and the pmu type in the sample. See my comment on Stephane's patch '[PATCH] perf: make perf.data more self-descriptive (v5)'.
Thanks,
-Robert
-- Advanced Micro Devices, Inc. Operating System Research Center
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