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    SubjectRe: [PATCH 1/3] add dma_coherent_write_sync to DMA API
    On Thu, 2011-09-01 at 11:57 +0200, Michał Mirosław wrote:
    > BTW, if there's no time limit on write buffers flushing, or if write
    > buffers can cause reordering of the writes, then the memory accesses
    > need to be managed just like non-DMA-coherent memory. So what differs
    > then in DMA-coherent vs non-DMA-coherent mappings then?

    My understanding is that ordering is preserved, but an ARM guy should
    probably verify that.

    IIUC, the write buffers could hold data indefinitely. As a practical
    matter other writes needing to go out to memory will force buffered
    data out eventually. Again, this is my understanding which may be
    faulty. My feeling is that this extended write buffering makes it
    hard to call the dma memory fully coherent, but other limitations on
    ARMv7 make the buffering hard to avoid.


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