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SubjectRe: [perf] enable raw OFFCORE_EVENTS for non-perf userspace
On Thu, 4 Aug 2011, Peter Zijlstra wrote:

> On Wed, 2011-08-03 at 12:05 -0400, Vince Weaver wrote:
>
> > diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
> > index 4ee3abf..28f9ca9 100644
> > --- a/arch/x86/kernel/cpu/perf_event.c
> > +++ b/arch/x86/kernel/cpu/perf_event.c
> > @@ -604,12 +604,8 @@ static int x86_setup_perfctr(struct perf_event *event)
> > return -EOPNOTSUPP;
> > }
> >
> > - /*
> > - * Do not allow config1 (extended registers) to propagate,
> > - * there's no sane user-space generalization yet:
> > - */
> > if (attr->type == PERF_TYPE_RAW)
> > - return 0;
> > + return x86_pmu_extra_regs(event->attr.config, event);
> >
> > if (attr->type == PERF_TYPE_HW_CACHE)
> > return set_ext_hw_attr(hwc, event);
>
>
> I'm inclined to merge this, aside from snb, the offcore stuff is
> actually quite usable now. Ingo can we somehow persuade you?

This would make me happy. The patch is more or less a revert of the patch
that disabled support in the first place, but if you need my signed-off-by
(I forgot it before) here it is

Signed-off-by: Vince Weaver <vweaver1@eecs.utk.edu>

> Anybody who knows how to program the snb offcore please tell. I mean we
> have all the code to poke at the right registers, and the SDM lists all
> the various bits that go where and a few constraints on how to combine
> said bits, but I've really no idea what any of it means.

I've added Stephane as I think he did some work on SandyBridge offcore.

Vince



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