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Subject[PATCH 2/2] x86: Enable monitor/mwait on Intel if BIOS hasn't already
Date
I have a Sandy Bridge machine with an Intel BIOS that enables
monitor/mwait on all but the boot CPU. With this patch, intel_idle
works.

Signed-off-by: Andy Lutomirski <luto@mit.edu>
---
arch/x86/kernel/cpu/intel.c | 20 ++++++++++++++++++++
1 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 6b20fef..a3339a1 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -487,6 +487,26 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
}
}
+
+ /* Enable monitor/mwait if BIOS didn't do it for us. */
+ if (!cpu_has(c, X86_FEATURE_MWAIT) && cpu_has(c, X86_FEATURE_XMM3)
+ && c->x86 >= 6 && !(c->x86 == 6 && c->x86_model < 0x1c)
+ && !(c->x86 == 0xf && c->x86_model < 3)) {
+ u64 misc_enable;
+ rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
+ misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT;
+
+ /*
+ * Some non-SSE3 cpus will #GP. We check for that,
+ * but it can't hurt to be safe.
+ */
+ wrmsr_safe(MSR_IA32_MISC_ENABLE, (u32)misc_enable,
+ (u32)(misc_enable >> 32));
+
+ /* Re-read monitor capability. */
+ if (cpuid_ecx(1) & 0x8)
+ set_cpu_cap(c, X86_FEATURE_MWAIT);
+ }
}

#ifdef CONFIG_X86_32
--
1.7.6


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