Messages in this thread | | | Date | Thu, 25 Aug 2011 12:07:44 -0500 (CDT) | From | Christoph Lameter <> | Subject | Re: [PATCH] memcg: remove unneeded preempt_disable |
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On Thu, 25 Aug 2011, James Bottomley wrote:
> >ARM seems to have these LDREX/STREX instructions for that purpose which > >seem to be used for generating atomic instructions without lockes. I > >guess > >other RISC architectures have similar means of doing it? > > Arm isn't really risc. Most don't. However even with ldrex/strex you need two instructions for rmw.
Well then what is "really risc"? RISC is an old beaten down marketing term AFAICT and ARM claims it too.
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