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SubjectRe: [PATCH 0/7] perf, x86: Implement AMD IBS
On 29.07.11 13:07:16, Peter Zijlstra wrote:
> On Thu, 2011-07-28 at 15:46 +0200, Robert Richter wrote:
> > This patch set adds support for AMD IBS to perf.
> > The approach is still to collect raw sample data which should be the
> > most important use case for application developers. The data format is
> > the same as described in the IBS register specification.
> That makes it hardware dependent right? I take it new hardware with IBS
> extensions adds output MSRs.

IBS is supposed to be architectural spec'ed, meaning there are no
family checks. IBS features are detected using cpuid.

So the version of the raw sampling data format could be specified with
the u32 capability variable. I could put the caps value to the raw
sample data too right after the size field. An additional advantage
would be that 64 bit values are memory alligned then.

The Branch Target Address register that has been added to newer cpus
could simply be extended to the raw data sample, the data would still
be backward compatible. Userland can detect it existence from the
sample size or (better) from the ibs caps.

> Anyway, I'll try and go over it again next week after reading the IBS
> hardware spec (again.. that stuff just won't stick to memory).
> I've got the BKDG for Fam10, is there anything more I should read?

Though it is treated architectural, it isn't in the AMD64 Architecture
Programmer's Manual (APM). The 10h BKDG is a good source, but extended
IBS features are described in the family 12h bkdg (same as for 15h)
and the capabilities are in the cpuid spec:


Advanced Micro Devices, Inc.
Operating System Research Center

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