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    Subject[PATCH 06/12] x86, mce: replace MCM_ to MCI_MISC_
    Follow other MCi_* register defines.
    Plus define MCI_MISC_ADDR_LSB() and MCI_MISC_ADDR_MODE().

    Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
    ---
    arch/x86/include/asm/mce.h | 17 +++++++++++------
    arch/x86/kernel/cpu/mcheck/mce.c | 4 ++--
    2 files changed, 13 insertions(+), 8 deletions(-)

    diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
    index 021979a..bbb328f 100644
    --- a/arch/x86/include/asm/mce.h
    +++ b/arch/x86/include/asm/mce.h
    @@ -8,6 +8,7 @@
    * Machine Check support for x86
    */

    +/* MCG_CAP register defines */
    #define MCG_BANKCNT_MASK 0xff /* Number of Banks */
    #define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */
    #define MCG_EXT_P (1ULL<<9) /* Extended registers available */
    @@ -17,10 +18,12 @@
    #define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
    #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */

    +/* MCG_STATUS register defines */
    #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
    #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
    #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */

    +/* MCi_STATUS register defines */
    #define MCI_STATUS_VAL (1ULL<<63) /* valid error */
    #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
    #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
    @@ -31,12 +34,14 @@
    #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
    #define MCI_STATUS_AR (1ULL<<55) /* Action required */

    -/* MISC register defines */
    -#define MCM_ADDR_SEGOFF 0 /* segment offset */
    -#define MCM_ADDR_LINEAR 1 /* linear address */
    -#define MCM_ADDR_PHYS 2 /* physical address */
    -#define MCM_ADDR_MEM 3 /* memory address */
    -#define MCM_ADDR_GENERIC 7 /* generic */
    +/* MCi_MISC register defines */
    +#define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f)
    +#define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7)
    +#define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */
    +#define MCI_MISC_ADDR_LINEAR 1 /* linear address */
    +#define MCI_MISC_ADDR_PHYS 2 /* physical address */
    +#define MCI_MISC_ADDR_MEM 3 /* memory address */
    +#define MCI_MISC_ADDR_GENERIC 7 /* generic */

    /* CTL2 register defines */
    #define MCI_CTL2_CMCI_EN (1ULL << 30)
    diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
    index e81d48b..e807508 100644
    --- a/arch/x86/kernel/cpu/mcheck/mce.c
    +++ b/arch/x86/kernel/cpu/mcheck/mce.c
    @@ -844,9 +844,9 @@ static int mce_usable_address(struct mce *m)
    {
    if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
    return 0;
    - if ((m->misc & 0x3f) > PAGE_SHIFT)
    + if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
    return 0;
    - if (((m->misc >> 6) & 7) != MCM_ADDR_PHYS)
    + if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
    return 0;
    return 1;
    }
    --
    1.7.1



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