Messages in this thread | | | Date | Sun, 05 Jun 2011 11:12:18 +0300 | From | Avi Kivity <> | Subject | Re: [PATCH v1 5/5] KVM: Expose a version 1 architectural PMU to guests |
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On 06/03/2011 05:41 PM, Peter Zijlstra wrote: > On Wed, 2011-05-11 at 11:55 -0400, Avi Kivity wrote: > > - counters that have PMI (interrupt) enabled stop counting after the > > interrupt is signalled. This is because we need one-shot samples > > that keep counting, which perf doesn't support yet > > You'll have to reprogram the thing anyway, since not all hardware has > the same counter width: > > [ 0.046996] Performance Events: AMD PMU driver. > [ 0.048998] ... bit width: 48 > > vs > > [ 0.026998] Performance Events: PEBS fmt0+, Core2 events, Intel PMU driver. > [ 0.026998] ... bit width: 40 > > simply letting the thing run will not behave in a consistent fashion.
I don't really follow. How is the bit width related?
We adjust for bit width during PMC read.
Though I agree for accurate emulation we do need to reprogram, so we can set the next overflow event at 2^bit_width. I doubt that anyone relies on this second overflow (even with 40 bits counting cycles, it takes far too long to overflow), still we have to emulate it.
> Or are you going to assume all software will properly read the cpuid > leaf and not assume bit width? > > Also, I can't seem to locate where you fill that cpuid-leaf, > kvm_pmu_cpuid_update() seems to read the entry, not write it.
We rely on host userspace to set up cpuid (and KVM_GET_SUPPORTED_CPUID to report to userspace what we support).
-- error compiling committee.c: too many arguments to function
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